SEMICONDUCTOR CODE-TO-VOLTAGE CONVERTER

V. Z. YAMPOLSKY, L. V. PERFILIEV

(Presented by the scientific seminar of the Department of Electric Drive and Automation of Industrial Installations)

In automated electric-drive systems with digital control devices, conversion of a code into a voltage or current is the principal type of conversion of digital quantities into analog ones. Conversion of a code into an analog quantity is always carried out by summing analog quantities. When electrical signals are summed, both currents and voltages are summed simultaneously; therefore, for convenience of classification, it is assumed that current summation takes place when the circuit is loaded by a low resistance, and voltage summation when the operating mode of the summing circuit is close to no-load operation [1].

The summation of analog quantities, taking into account the “weight” of each digit of the code being converted, may be performed in a series or parallel form. The desire to reduce the requirements on the quality of switches and to eliminate the need for their careful insulation and shielding has given an advantage to various converter circuits with parallel connection of the digits.

In parallel conversion, all digits of the code are applied simultaneously to the summing circuit. The result of the conversion is represented as a certain sum of the “weights” in those digits of the code being converted in which a one is present. The output signal of each “digit” converter is proportional to the “weight” of the given digit, that is, for binary codes, to the quantity $2^i$, where $i$ is the ordinal number of the digit.

The development of parallel circuits was stimulated by the need to replace mechanical switches with contactless switches, which possess high reliability and speed, but are inferior to the former in the level of their own interference and in the simplicity of operation control.

The input and output circuits of a contactless switch are usually galvanically connected with one another, with the corresponding circuits of other switches, and with the power supply. Because of these parasitic galvanic connections, the use of contactless switches in multidigit series circuits is practically impossible. In parallel circuits, galvanic connections play a considerably smaller role, since the switches in any case must be connected to one or two buses. In addition, with series connection of individual ...

the parasitic emf’s and switch resistances of the digits are summed, whereas with parallel connection their total effect does not exceed the effect of the parasitic parameters of a single binary switch. Parallel converters are among the fastest-acting and, when electronic keys are used, make it possible to reduce the time of one conversion cycle to several microseconds.

A detailed analysis of approximate and exact parallel converters is carried out in [1, 2, 3]. The present paper sets forth an engineering method for calculating an exact parallel code-to-voltage converter, proposes a version of circuit implementation of such a converter using contactless semiconductor keys, and analyzes the main errors of the proposed circuit.

Calculation of the converter parameters

Calculation of the parameters of a code-to-voltage converter reduces to determining the values of the “weighting” resistances of the summing circuit and the value of the voltage of the reference power supply for specified load-parameter values. Here the load parameters are understood to mean the load resistance \(R_{\text{н}}\) and the amplitude of the converted signal, which is specified in the form of a current or voltage. When the converter is used in automated electric-drive systems, its load is most often the control windings of electromechanical or magnetic amplifiers. The converter parameters obtained as a result of the calculation must, with a specified degree of accuracy, provide on the amplifier control winding a voltage or current proportional to the code being converted.

Fig. 1.

The exact parallel circuit is shown in Fig. 1. It consists of a star-connected system of resistances \(2^i R\) \((i = 0,1,2,\ldots,n-1)\), where \(n\) is the maximum number of digits of the code being converted, and a system of keys that connect the arms of the star either to the reference voltage source \(E_{\text{э}}\), or to “ground.” In this case, for any combination of states—

... switches, the output resistance of the circuit remains constant, thereby ensuring a linear correspondence between the codes of the numbers being converted and the output voltages of the converter.

The parameters of an accurate parallel converter can be determined from equation [2]

\[ U_{\text{out}} = E_{\text{e}} \frac{\sum x_i g_i}{\sum g_i} = E_{\text{e}} \frac{G_{\text{unit}}}{\sum g_i} \sum x_i a_i, \tag{1} \]

where \(U_{\text{out}}\) is the output voltage of the converter,
\(E_{\text{e}}\) is the voltage of the reference power source,
\(G_{\text{unit}}\) is a certain unit conductance,
\(x_i\) is 1 or 0 depending on the position of the switch of the \(i\)-th digit,
\(g_i\) is the conductance of the \(i\)-th digit,
\(a_i\) are the weighting coefficients of the digits,
\(i = 1, 2, \ldots, n\),
\(n\) is the number of digits of the code being converted.

In this equation the output voltage of the converter \(U_{\text{out}}\) is related to the value \(E_{\text{e}}\) through the aggregate of the state values of the digit switches \(x_i\) and the digit (“weighting”) conductances \(g_i\). Despite the generality of this equation, its use for calculating converter parameters appears inconvenient because of the need first to determine the set of values \(a_i\) and \(g_i\). In the absence of sufficient experience, the latter may lead to converter parameters that are unfavorable or completely unsuitable for technical implementation. Only after two or three recalculations can the designer obtain an acceptable solution. In addition, to take the load parameters into account an additional recalculation is required.

The method of calculating a converter of this type can be substantially simplified by using a somewhat different approach. The special feature of the proposed approach is that the derivation of the equation

\[ U_{\text{out}} = f(E_{\text{e}}) \]

is carried out with allowance for the load parameters not for the general case, but for a particular case—the conversion of the code combination 00...01 (a one is present only in the least significant digit of the code).

Fig. 2.

The converter circuit corresponding to this particular case is shown in Fig. 2a. The output voltage of the converter corresponding to a one in the least significant digit is denoted by \(\Delta U_{\text{out}}\) and characterizes the resolving capability of the converter. The resolving capability of the converter is related to the amplitude of the conver...

of the signal being converted, specified in the form of currents or voltages, by the relations

\[ \Delta U_{\text{out}}=\frac{U_{\max}-U_{\min}}{2^n-1}; \]

\[ \Delta I_{\text{out}}=\frac{I_{\max}-I_{\min}}{2^n-1}. \tag{2} \]

Transforming, for convenience of consideration, the circuit of Fig. 2a to the form shown in Fig. 2b, one can, from Kirchhoff’s first law written for the node of the resistance star, obtain the following equation

\[ \frac{E_{\text{e}}-\Delta U_{\text{out}}}{2^{n-1}R} = \Delta U_{\text{out}} \left( \frac{1}{R_{\text{l}}} + \frac{1}{R}\sum_{i=0}^{n-2}2^{-i} \right), \tag{3} \]

where \(R\) is the “weight” resistance of the most significant digit of the converter,
\(R_{\text{l}}\) is the load resistance.

After elementary transformations we obtain

\[ \Delta U_{\text{out}} = \frac{E_{\text{e}}}{ 1+\dfrac{2^{n-1}R}{R_{\text{l}}} + 2^{n-1}\sum_{i=0}^{n-2}2^{-i} }. \tag{4} \]

From the condition of linearity of the converter characteristic, the particular result obtained is easily generalized for any \(U_{\text{out}}\):

\[ U_{\text{out}} = N\cdot \Delta U_{\text{out}} = \frac{N\cdot E_{\text{e}}}{ 1+\dfrac{2^{n-1}R}{R_{\text{l}}} + 2^{n-1}\sum_{i=0}^{n-2}2^{-i} }, \tag{5} \]

where \(N\) is the decimal equivalent of the binary code being converted.

Rewriting equation (5) with respect to \(R\), we obtain the equation of the converter “weight” characteristic

\[ R = \frac{E_{\text{e}}\cdot R_{\text{l}}}{\Delta U_{\text{out}}\cdot 2^{n-1}} - R_{\text{l}}\sum_{i=0}^{n-1}2^{-i}. \tag{6} \]

The converter “weight” characteristic is a straight line in the coordinate axes \(R\) and \(E_{\text{e}}\), whose slope and point of intersection with the abscissa axis are completely determined by the load parameters: the resistance \(R_{\text{l}}\) and the amplitude of the signal being converted, \(U_{\max}-U_{\min}\) or \(I_{\max}-I_{\min}\).

A family of “weight” characteristics of a 10-bit code-to-voltage converter for various load parameters is presented in Fig. 3. The load of the converter consists of the control windings of commercially produced electric-machine amplifiers, whose parameters are indicated in the corresponding columns of Table 1.

The given family of “weight” characteristics makes it possible to determine directly from the graph the value of the resistance \(R\) for any values of the voltage \(E_{\text{e}}\).

For \(n>8\), one may use the approximate equation of the “weight” characteristic

\[ R=\frac{E_{\text{e}}\cdot R_{\text{l}}}{\Delta U_{\text{out}}\cdot 2^{n-1}}-2R_{\text{l}}, \tag{7} \]

Since already at \(n=8\) the sum of the terms of the geometric progression

\[ \sum_{i=0}^{7} 2^{-i} \]

is equal to 2 with an accuracy of one percent. The greater \(n\) is, the more accurately equation (7) approximates (6). At \(n=10\), the results of calculation by equation (7) differ by only \(0.04\%\).

Fig. 3.

Table 1

Continuation of Table 1

In the case where the amplitude of the load signal is specified in the form of a current, equation (6) is conveniently written in the following form

\[ R=\frac{E_{\mathrm{e}}}{\Delta I_{\mathrm{out}}\cdot 2^{n-1}} - R_{\mathrm{L}}\sum_{i=0}^{n-1}2^{-i}, \tag{8} \]

where

\[ \Delta I_{\mathrm{out}}=\frac{\Delta U_{\mathrm{out}}}{R_{\mathrm{L}}} \]

is the increment of current in the load per unit of the least significant bit of the code, or, equivalently, the current resolution of the converter.

The condition for the physical realizability of the code-to-voltage converter for the specified load parameters is satisfaction of the inequality

\[ \frac{E_{\mathrm{e}}\cdot R_{\mathrm{L}}}{\Delta U_{\mathrm{out}}\cdot 2^{n-1}} - R_{\mathrm{L}}\sum_{i=0}^{n-1}2^{-i}>0. \tag{9} \]

Inequality (9) is satisfied for all values \(E_{\mathrm{e}}>E_{\mathrm{e}0}\) \((k=1,2,\ldots,\) Fig. 3), that is, for all values of \(E_{\mathrm{e}}\) to the right of the point of intersection of the “weight” characteristic with the abscissa axis. For \(E_{\mathrm{e}}<E_{\mathrm{e}0}\) (dashed portions of the characteristics), the “weight” resistances fall into the region of negative values and, consequently, make the converter physically unrealizable.

In order to increase the accuracy of the converter, it is advisable to choose \(E_{\mathrm{e}}\) as large as possible, since in this case the magnitude of the “weight” resistances increases, which reduces the influence of the parasitic parameters of actual converter circuits. For the same reasons, the sloping characteristics 11, 12, 13, and 14 are undesirable. Loads corresponding to straight lines 11, 12, 13, and 14 are characterized by a small resistance value and a large current amplitude; therefore, for them, converters of the current type [1] should be used.

Using the relationships obtained, the calculation of the code-to-voltage converter reduces to the following:

1. Two arbitrary values of \(E_{\mathrm{e}}\) are specified and, from equation 6 or 8 (depending on the form in which the load parameters are specified), the corresponding values of \(R\) are determined.

2. In the coordinate axes \(R\) and \(E_{\mathrm{e}}\), the “weight” characteristic of the converter is drawn through the points obtained; with its aid, the value of the voltage of the reference source \(E_{\mathrm{e}1}\) is selected and the “weight” resistance of the most significant bit of the converter, \(R_1\), is determined (Fig. 3).

3. The “weight” resistances of the remaining bits are found by elementary recalculation

\[ R_i=2^{\,n-i}R_1; \qquad (i=1,2,\ldots,n). \]

Variant of the Circuit Implementation of the Converter

In implementing precise parallel converters, the greatest difficulties arise in selecting contactless transfer switches for switching the output stages. Since they possess finite resistances in the conducting and nonconducting directions, semiconductor (diode and triode) switching circuits introduce additional errors into the operation of the converter. Ensuring strictly constant transfer resistances of the switches is an unrealistic task; therefore one seeks to make the resistance of a closed switch very

small, and the resistance when open as large as possible. The best parameters (in comparison with diode switches) are obtained by switches based on alloyed semiconductor triodes. The principle of constructing such switches is based on using the low transition resistance of the triode in the deep-saturation mode and the high resistance of the emitter-collector junction of the triode in the off state in the presence of an external positive bias.

Figure 4 shows the circuit of an \(n\)-digit parallel binary-code-to-voltage converter using a precision summing circuit, in which the digit resistances are switched by contactless transfer switches based on semiconductor triodes proposed by the authors.

Fig. 4.

In this circuit the triodes \(T_1 - T_n\) are contactless transfer switches for connecting the “weight” resistances of the digits \(2^0R - 2^{n-1}R\) to the reference stabilized power source of the converter \(E_z\), hereinafter called the switching triodes. The bases of the switching triodes are connected through resistances \(R_c\) to the source of external bias \(+U_{\mathrm{bias}}\) in order to suppress dark currents and, consequently, to increase the resistance of the triode in the off state.

The parallel code being converted controls the state of the switching triodes; for this purpose their bases are connected to the right-hand outputs of the flip-flops of the memory register. In each digit a shunting triode \(T_{\mathrm{sh}}\) is connected in parallel with the collector resistance \(R_k\) of the switching triode.

The state of the shunting triodes \(T_{\mathrm{sh}(1)} \div T_{\mathrm{sh}(n)}\) is controlled by the code inverse to the one being converted. The inverse of the converted code is always present at the left-hand (inverted) outputs of the flip-flops of the memory registers, which are connected to the bases of the shunting triodes.

If a “1” is present in the \(i\)-th digit of the code being converted, then the switching triode of the \(i\)-th digit is opened by the negative potential from the right-hand output of the flip-flop of the memory register, while the shunting triode of this digit will be closed by the positive potential from the inverted output of the flip-flop. In this case the “weight” resistance of the \(i\)-th digit is connected through the load resistance \(R_n\) to the full voltage \(E_z\). If, however, a “0” is present in the \(i\)-th digit of the code being converted,

then the switching triode of the \(i\)-th digit will be closed, and the shunting one open. In this case the “weight” resistance of the \(i\)-th digit is connected in parallel with the load resistance through the open triode \(T_{\text{sh}(i)}\). In the absence of the shunting triode, the “weight” resistance would be connected in parallel with the load resistance \(R_{\text{н}}\) through the resistance \(R_{\text{к}}\), which would lead to a change in the output resistance of the converter circuit and, consequently, to a violation of its linearity.

Thus, the proposed circuit of a digit switching key, consisting of the triode \(T_i\) and \(T_{\text{sh}(i)}\) (switching and shunting), ensures switching of the “weight” resistance of the \(i\)-th digit from the plus to the minus of the reference voltage source \(E_{\text{э}}\) with a minimum error determined by the resistance of the triode in the deep-saturation mode.

Taking into account that all shunting triodes operate in the emitter-follower mode, for their complete opening it is necessary to satisfy the condition \(U_{\text{in}} > E_{\text{э}}\), where \(U_{\text{in}}\) is the input-signal voltage at the bases of the shunting triodes.

Equivalent Circuit

To estimate the errors introduced by triode switches, let us consider the equivalent circuit of the semiconductor converter (Fig. 5), which corresponds to the presence of a one only in the least significant digit of the code.

Fig. 5.

In the equivalent circuit, the semiconductor triodes are represented by the corresponding equivalent resistances: \(R_1\) and \(R_2\) are the resistances of the switching and shunting triodes in the saturation mode, and \(R_3\) and \(R_4\) are the resistances of these same triodes in the closed state. The magnitude of the resistance of a triode in the saturation mode is a nonlinear function of the magnitude of the collector current and increases as the current decreases.

As shown by experimental investigations of type P26 semiconductor triodes in the range of collector voltages \(8\)—\(90\ \text{V}\), collector currents from \(1\) to \(200\ \text{mA}\), in the presence of external positive bias, the values of the corresponding resistances of the equivalent circuit vary within the limits:

\[ R_1 = 1 \div 5\ \Omega \]

\[ R_2 = 15 \div 40\ \Omega \]

\[ R_3, R_4 = 1 \div 3\ \text{M}\Omega \]

Semiconductor triodes of the type considered are the most suitable for implementing code-to-voltage converters, since they make it possible to construct circuits with the greatest range of voltages of the reference sources—up to \(100\ \text{V}\).

Transforming the equivalent circuit according to the laws of electrical engineering to the form shown in Fig. 2b, from equation (4) one can estimate the degree of influence of the parasitic resistances of the semiconductor switches on the accuracy of the converter.

Calculations show that for load parameters whose “weight” characteristics lie above line 9 (Fig. 3), with co-

With an appropriate choice of the value of \(E_{\mathrm{e}}\), the error of the proposed circuit does not exceed \(0.05\%\).

As can be seen from the equivalent circuit, the largest error in the value of the digit resistances is introduced by the resistances \(R_2\), and, consequently, the total error of the converter will be the greater, the more shunting triodes are found to be in the saturation mode.

The equivalent circuit under consideration has the maximum error (in all digits of the circuit, except the least significant one, the resistance \(R_2\) is present), and the error estimate obtained for it is an upper limit for the given converter.

REFERENCES

1. E. I. Gitis. Information Converters for Electronic Digital Computing Devices, GEI, 1961.

2. K. A. Netrebenko. Digital Automatic Compensators, GEI, 1961.

3. V. B. Smolov. Computing Converters with Digitally Controlled Resistances. GEI, 1961.