APPLICATION OF A READ-ONLY MEMORY IN CIRCUITS FOR STABILIZING THE RADIATION INTENSITY OF A BETATRON

V. M. Razin, V. L. Ryabukhin

(Presented by the scientific seminar of the Department of Mathematical and Computing Instruments and Devices)

In most devices currently in existence for regulating the radiation intensity of a betatron, the phase of the injection pulse, defined as [1], is used as the controlled parameter:

\[ t_i=\frac{10^4\sqrt{U_i(U_i+1.02)}}{3r_0\omega H_m}, \tag{1} \]

where \(t_i\) is the time in sec;

\(\omega\) is the frequency of the supply network feeding the electromagnet;

\(U_i\) is the injection voltage in megavolts;

\(H_m\) is the magnetic-field strength on the equilibrium orbit, in oersteds;

\(r_0\) is the radius of the equilibrium orbit, in cm.

Expression (1) can be rewritten in the form

\[ t_i=f(U_i)\cdot f(H_m), \tag{2} \]

where

\[ f(U_i)=\sqrt{U_i(U_i+1.02)}, \tag{3} \]

\[ f(H_m)=\frac{10^4}{3r_0\omega H_m}=\frac{k}{H_m}. \tag{4} \]

To solve equation (2), a computing device was developed in which the values of the functions (3) and (4) are found by means of a read-only memory (ROM).

The capacity and speed of such a ROM may be comparatively small, since the betatron operates at a frequency of 50 Hz, and the range of variation of the functions (2) and (3) is determined by fluctuations of the line voltage. Therefore, to find the values of (2) and (3) with an error of no more than 0.1%, it is sufficient to have two ROMs with a capacity of 256 ten-bit binary numbers, which will correspond to variations of \(U_i\) and \(H_m\) by \(\pm 12.5\%\). By proper selection of the scale factors in coding the functions, the number of digits of the numbers stored in the ROM can be reduced to 8, and the two most significant digits, equal to 1, can be taken into account when reading information from the memory device.

Of decisive importance in designing the memory device is the choice of the control circuit, whose physical size and cost usually exceed many times the size and cost of the memory block itself. The main unit of the control circuit is the address decoding system of the ROM, which must ensure the stability

sampling of information from the SM under conditions of maximum logical simplicity of the circuit, a minimum number of active elements, and a high efficiency factor.

These requirements are met by a system for decoding the address with two-sided coordinate control of the storage matrix [2], which has a small number of active drivers, a high efficiency, and a large information-packing factor of the cores. Two-sided control is carried out both along the \(x\) coordinate and along the \(y\) coordinate. To ensure a small spread in the parameters of the address-current pulses, in order to obtain identical readout signals and reliable operation of the memory device, the principle of multi-cycle selection of a number from the storage device was used [3].

The permanent storage device, whose block diagram is shown in Fig. 1, consists of a storage matrix made on ferrite cores with a rectangular hysteresis loop, and a control circuit consisting of an address system and readout amplifiers.

Fig. 1. Block diagram of a permanent storage device

Let us consider the operation of the PSD when selecting values of the function \(f(U_i)\). Before operation begins, all the cores of the matrix are set by a special driver to the initial state “1.” In the second cycle, the code of the high-order bits of the varying part of the values \(U_i\), stored in the register, is fed to decoders DS3 and DS4 (all decoders have 4 outputs). According to this code, one of the drivers \(\Phi_9\!-\!\Phi_{12}\), \(\Phi_{13}\!-\!\Phi_{16}\) is actuated, as a result of which all the cores of one of the horizontal readout buses of the matrix become remagnetized

to state “0.” In the third clock cycle, the code of the lower-order digits is fed to decoders DSh1 and DSh2, as a result of which one of the formers \(\Phi_1 \div \Phi_4\) and \(\Phi_5 \div \Phi_8\) is triggered and one of the 16 vertical write buses is selected. The write buses pass only through those cores in which a “1” is to be written. Since the direction of the magnetic field produced by the currents when the matrix is set to its initial state and during writing is opposite to the direction of the magnetic field during reading, in the third clock cycle only the cores of the horizontal row selected in the second clock cycle will be remagnetized to state “1”; as a result, the value of function (3) corresponding to the input code \(U_i\) is written in it. In the fourth clock cycle, the code of the higher-order digits is again applied to decoders DSh3 and DSh4, and the recorded number is read out. An advantage of a ROM with four-cycle number selection is that the number of cores remagnetized by the write and read current amplifiers does not exceed the word length of the stored numbers, owing to which the circuit is not critical with respect to the amplitude of the exciting currents.

Reading is carried out twice—in the second and fourth clock cycles; therefore, to ensure correct operation of the ROM, additional switching cells are installed in series with the read amplifiers, which are unlocked only in the fourth clock cycle.

In the base circuit of the read amplifiers, an interference signal may arise, caused by the reading of “0” from the cores of the digits threaded by the common read conductor. To compensate interference, one compensating core is introduced into the base circuit of the amplifiers; as a result, one row of compensating cores is sufficient for the entire matrix. The outputs of the formers \(\Phi_9 \div \Phi_{12}\) enter the compensating row (point \(a\)) and go out to the corresponding groups of read buses of the matrix (point \(b\)). Interference compensation during writing is not required.

To store the values of two functions (3) and (4), the write and read buses of the corresponding matrices are connected in series. In this case, each matrix requires its own read amplifiers. The number is issued from the required matrix by gating the corresponding read amplifiers.

The ROM construction method considered provides high operating reliability of the device and is highly economical. When the range of variation of the values \(U_i\) and \(H_m\) is increased to \(\pm 25\%\), the number of address formers will increase to 20, and instead of one of the decoders with 4 outputs it is necessary to introduce a decoder with 8 outputs. The number of diodes used to eliminate parasitic circuits will increase from 32 to 48.

Figure 2 shows the circuit of the address formers. The blocking oscillator (\(T_1\)—\(T_2\)) is started by a negative pulse taken from the decoder output and delivers to the load a pulse with an amplitude of \(40 \div 50\) mA and a duration of \(3 \div 4\) \(\mu\)sec. The transformer is wound on an oxyferrite core M-1000 with a diameter of 7 mm. The output formers are assembled on triodes of type P601, providing a pulse current of 1 A. Resistors \(R_5\) and \(R_7\), of 1 ohm, compensate the spread in triode parameters and increase the temperature range of operation of the circuit. Resistor \(R_6\) is included to increase the speed and prevent failure of transistor \(T_3\). Diodes of types D310, D220, and D223 may be used for switching the matrix address buses.

Figure 3 shows the circuit of the read amplifiers. Triode \(T_3\) operates as a switch. In the normal state, the triodes of the read amplifiers—

Fig. 2. Schematic circuit of the address shapers

Fig. 3. Schematic circuit of the readout amplifiers

In the diagram: “compensating cores.”

are closed by a voltage of \(+6\) V and are opened in the fourth cycle, when a strobing pulse is applied to the base of triode \(T_3\). In the matrices, VT-5 cores of 3 mm diameter are used. The number of turns of the removable winding is 8–10. The write, read, and reset-to-initial-state windings have one turn each.

It should be noted that the ROM operating cycle can be shortened to 3 cycles by eliminating the mode in which the matrix is reset to its initial state; in this case, normal operation of the device begins after a preliminary sampling of all numbers from the ROM.

The developed circuits of the address formers and read amplifiers do not require preliminary selection of transistors. The permissible range of variation of the supply voltages is \(\pm 10\%\). Long-term operation of the developed ROM has shown the high reliability of its performance.

REFERENCES

1. V. M. Razin. Izvestiya TPI, vol. 87, 1957, 206–216.
2. V. P. Isaev, A. V. Gusev. In: Collection of articles edited by L. P. Kraizmer, “Operative and Permanent Storage Devices.” Energiya Publishing House, 1965, 109–117.
3. E. I. Gurvich and L. B. Shchukin. Ferrotransistor Elements and Their Application in Digital Automatic Devices. Gosenergoizdat, 1963, pp. 103–107.