VOLTAGE-TO-CODE CONVERTER FOR AN AUTOMATIC CONTROL SYSTEM

V. M. Tanaseichuk, Ya. I. Kapishchii, V. M. Razin,
N. P. Baida

Code-pulse analog-to-digital converters (ADCs) have become the most widespread in automatic control systems (ACS) [1–3]. To obtain the required speed and accuracy in ACS, code-pulse ADCs are most often used, with a digital-to-analog converter (DAC) included in their feedback circuit. The compensating voltage \(U_k\) is generated by the digital-to-analog converter according to a specified program. When each digit of the DAC is switched on, the compensating voltage increases by an amount equal to the “weight” of this digit in the code used. The most widespread codes are 2421, 4221, and 5221.

During the conversion process, all digits of the DAC are switched on sequentially. When \(U_k > U_x\), the last digit is switched off and the next one is switched on. Usually, the generation of \(U_k\) begins with the most significant digit.

For a known measurement limit \(U_{\max}\) and a selected value of the unit of the least significant digit (the quantization step by the level \(U_k\)), the number of ADC digits and, correspondingly, the number of conversion cycles is determined by the formula:

\[ n=\log_2 U_{\max}. \tag{1} \]

With binary-coded decimal coding, relation (1) has the form

\[ n=4N, \tag{1a} \]

where \(N\) is the number of binary-coded decimal decades.

Code-pulse ADCs most fully satisfy the principal requirements imposed on ADCs that are to be used in ACS. A drawback of such ADCs is the comparatively high complexity of their implementation in comparison with time-pulse ADCs. The distributor for specifying the program of generating \(U_k\) sharply increases the amount of equipment. When the distributor is implemented on a counter with a decoder, the following condition must be satisfied for the number of counter digits:

\[ \begin{aligned} \text{a)}\quad & m \geq \log_2 n;\\ \text{b)}\quad & m \geq 4N, \end{aligned} \tag{2} \]

a — for binary coding;
b — for binary-coded decimal coding.

It is possible to construct an ADC without a distributor. In this case \(U_k\) begins to be generated from 0 and at each clock cycle is increased by one quantization step in level. However, the conversion time then increases sharply. To convert the voltage \(U_x\), it is necessary to have

\[ \frac{U_x}{U_{\mathrm{kv}}} \]

clock cycles, where \(U_{\mathrm{kv}}\) is the voltage equal to the quantization step.

Fig. 1. Plot of the generation of \(U_k\)

A certain modification of the code-pulse method of analog-to-digital conversion is possible, which considerably simplifies the overall ADC circuit while retaining high speed.

The generation of the compensating voltage begins with the most significant decade and is carried out in each decade according to the decimal law, starting from the maximum value, in equal steps toward reduction. The number of clock cycles for generating the compensating voltage is determined by the formula:

\[ n=\sum_{\substack{i=0\div 9\\ j=0\div m}}(10-\alpha_{ij})+1, \tag{3} \]

where

\(n\) — number of clock cycles,
\(i\) — the digit written in the \(j\)-th decade,
\(j\) — decade number,
\(m\) — number of decades.

The plot of the generation of \(U_k\) is presented in Fig. 1, where
\(U_k\) — compensating voltage,

$\widetilde{TU}$ — clock pulses,
$U_{\text{н0}}$ — pulses from the zero element.

The operation of the converter begins with the processing of the compensating voltage of the most significant decade. $U_{\text{k}}$ changes in the following order:

\[ U_{\text{k}1}=Q_1\cdot a_9;\quad U_{\text{k}2}=Q_1\cdot a_8;\quad U_{\text{k}3}=Q_1\cdot a_7;\ldots \]

\[ U_{kn}=Q_1\cdot a_{10-n_1}, \]

where $Q_1$ is the “weight” of the unit of the least significant digit for the most significant decade; $a_{10-n_1}$ is the digit corresponding to a number of clock pulses equal to $n_1$.

When $U_{\text{k}}>U_x$, the signal from the zero element disconnects the first decade from further operation and switches the second decade into the processing of the compensating voltage; this decade processes the compensating voltage analogously to the first decade.

When $U_{\text{k}}>U_x$, the third decade is connected, and so on. The voltage $U_{\text{k}}$ after processing by all three decades will be equal to:

\[ U_{\text{k}}=Q_1\cdot a_{10-n_1}+Q_2\cdot a_{10-n_2}+Q_3\cdot a_{10-n_3}, \tag{4} \]

where

\[ \begin{aligned} Q_1&\text{ is the “weight” of the unit of the least significant digit of the 1st decade;}\\ Q_2&\text{ is the “weight” of the unit of the least significant digit of the 2nd decade;}\\ Q_3&\text{ is the “weight” of the unit of the least significant digit of the 3rd decade.} \end{aligned} \]

Fig. 2. Block diagram of the ADC

\(a_{10-n_1}\) is the digit recorded in the 1st decade with the number of operating pulses \(n_1\);

\(a_{10-n_2}\) is the digit recorded in the 2nd decade with the number of operating pulses \(n_2\);

\(a_{10-n_3}\) is the digit recorded in the 3rd decade with the number of operating pulses \(n_3\).

The block diagram of the ADC is shown in Fig. 2.

The converter consists of a controlled voltage divider, three counting decades operating in subtraction mode, a three-input distributor, a zero detector, and a control unit.

Clock pulses are applied to the inputs of the counting decades through coincidence circuits \(C_{n_1}\), \(C_{n_2}\), \(C_{n_3}\), each of which is controlled by the corresponding output of the distributor.

The circuit operates as follows.

In the initial state all flip-flops of the counting decades are set to the “0” state, and the compensation voltage is equal to zero. The “start” signal sets the distributor to the state in which the coincidence circuit \(C_{n_1}\) is opened. The 1st counting decade begins to operate. The voltage \(U_k\) changes in the following order: 0.9 V, 0.8 V, and so on. When \(U_k < U_x\), a pulse from the zero detector sets the distributor to a state in which \(C_{n_1}\) is closed and \(C_{n_2}\) is opened. The 2nd counting decade begins to operate. In this case, in a manner analogous to that described above, the second digit of the compensating voltage is worked out, i.e., beginning with the most significant digit. When \(U_k < U_x\), the signal from the zero detector closes the second coincidence circuit and opens the third. The third decade operates analogously to the first two.

Example of measuring \(U_x = 7.63\) V.

Table 1

The ADC described above has a considerably smaller number of elements than the commonly used pulse-code ADCs, since a distributor is required that contains only one output for each decade.

The average speed of the ADC (assuming that the possibility of occurrence in each decade of any of the 10 digits is equally probable) is

\[ t_{\mathrm{av}} = N \cdot \frac{t_{\max} + t_{\min}}{2} = 5N \text{ cycles}. \tag{5} \]

Comparing the obtained value with formula (1a), it may be noted that processing each decade in the proposed ADC requires 1 cycle more than in an ordinary pulse-code ADC.

REFERENCES

1. E. A. Drozdov, A. P. Pyatibratov. Automatic Conversion and Encoding of Information. “Sovetskoe radio,” Moscow, 1964.

2. K. A. Netrebenko. Digital Automatic Compensators. Gosenergoizdat, 1961.

3. E. I. Kondyukova, B. E. Red’kin. Analog-to-Digital Converters of Automatic-Control Systems. Energiya, Moscow, 1967.