On the Issue of Resetting the Counter

A. V. Trikhanov

(Presented by the scientific seminar of the Department of Computer Engineering)

A multi-digit counter is composed on the basis of single-digit counters, flip-flops with counting inputs. The carry signal into a given digit is formed when the preceding digit passes into the zero position (upon reset).

When a multi-digit counter is reset, all flip-flops are transferred to the zero state. From Fig. 1 it is clear that, if the duration of the reset signal is equal to \(t_1 - t_0\), then a carry signal is formed from the output of the flip-flop being reset, and the flip-flop of the next digit is set to the one state.

Fig. 1. Timing relationships when resetting a flip-flop

This may fail to occur if, as is evident from the figure, the reset signal overlaps in duration \((t_2 - t_0)\) the trailing edge of the output signal [5].

In addition, other reset methods are known. They can be classified into several groups.

The first group should include those methods in which the carry signal and the reset signal act simultaneously on the flip-flop. Moreover, if one has in mind a semiconductor flip-flop, then the carry signal usually takes the form of a positive pulse. It acts on the base of the triode that is open during reset. Reset will, of course, be more effective if the reset signal is applied to the above-mentioned base. It follows from this that

Fig. 2. Group reset by means of an additional transistor

this signal must be negative. The effect of the reset signal on the flip-flop may also be different. For example, [4] describes a reset method using an additional transistor (Fig. 2), which in the normal state is open. When a positive pulse is applied to its base, the transistor closes and breaks the supply circuit of one of the transistors of each counter flip-flop. The flip-flops pass into the zero state.

Fig. 3. Counter with reset effected by the counting process

The second group of reset methods comprises methods that make use of the counter’s property of passing into the zero state in the process of counting. These methods may be called indirect. Of the possible methods of this group, the simplest [6] consists in first filling the counter completely with ones, as a register, and then applying a one signal to the zero input of the least significant stage (Fig. 3). Such a reset requires a time equal to \(\tau(n+1)\), where \(n\) is the number of stages in the counter and \(\tau\) is the flip-flop switching time.

Since the least significant digit of the counter operates at a higher frequency than the other digits, it is undesirable to complicate the circuit of that digit. It turns out that one input (the zero input) of this digit is sufficient.

Fig. 4. Counter with reset by means of the counting process. First modification

Consequently, instead of entering a one and then applying a signal to the zero input of the first digit of the counter, it is only necessary to reset it. When the first digit is reset (Fig. 4), all the others are set to the one states. Next, a signal is applied to the zero input of the second digit. Such a reset takes a time smaller by \(\tau\), as compared with the previous method, \(\tau n\).

Fig. 5. Counter with reset by means of the counting process. Second modification

The application of the signal to the zero input in the 2nd clock cycle can be shifted by one more digit toward the more significant digits (Fig. 5).

In the preceding case, after the first reset cycle the second digit will be either in the one state or in the zero state. This, of course—

Fig. 6. Counter with reset by means of the use of inhibit elements

but this will be when no signal (with the exception of the carry signal) is applied to it. All the other stages during this clock interval must be treated in the same way as in the preceding case.

During the second clock interval a signal should be applied to the zero input of the 2nd stage. If it was in the one state, then the counter will be reset; if it was in the zero state, it will not.

Fig. 7. Counter with resetting by using gates.

In order that, in this case, the signal should enter the 3rd stage, and specifically its zero input, a gate controlled by the inverse output of the second stage must be provided before this input.

In the latter case the reset time is reduced by another \(\tau\) and will be equal to \(\tau(n-1)\). It may be that the possibilities of two-clock resetting have not been fully utilized here.

Fig. 8. Carry-signal transmission circuit.

The third group includes methods characteristic of resetting shift registers [3]. As is known, in these methods the transmission of the carry signal is blocked by means of gates. The gates are closed during resetting.

On this basis reset circuits for a counter have been constructed in which noncoincidence gates are used—more precisely, inhibit elements [1]—and reset circuits in which gates are used [2]. The first variant is shown in Fig. 6, the second in Fig. 7. With these methods the counter is reset in time \(\tau\). It should be noted that as the inhibit element one may use coupling elements between flip-flops—differentiating circuits and semiconductor diodes which pass, to the bases of the triodes of the flip-flops, pulses of usually positive polarity (Fig. 8).

Input 2 is then used as the inhibiting input. When a negative pulse is applied to it, the diodes will be closed. The inhibit element does not pass the signal applied to input 1. When there is no reset, the inhibit elements are open and the counter operates normally in the counting mode.

Finally, combined methods may be placed in a fourth group.

References

1. N. G. Bruevich, B. G. Dostupov. Fundamentals of the Theory of Counting-and-Deciding Devices. “Sov. Radio,” Moscow, 1964.

2. E. N. Vavilov, G. P. Portnoi. Synthesis of Circuits of Electronic Digital Machines. Publishing House “Sov. Radio,” Moscow, 1963.

3. Laboratory Practicum for the Course “Discrete-Action Computing Machines.” Edited by V. B. Smolov and N. A. Smirnova. “Higher School,” Moscow, 1967.

4. E. M. Martynov. Contactless Switching Devices. GEI, Moscow–Leningrad, 1961.

5. V. A. Plisko. Elements of Digital Machines. Voenizdat, Moscow, 1965.

6. Technical Description of the Minsk-2 Electronic Computer. TsSU USSR, 1963.