Efficiency and Reliability of Instrument-Based Testing of Digital Devices
Abstract Generated abstract
The paper examines how to define and calculate the efficiency and reliability of instrument-based monitoring circuits for digital devices. Using a state table for combinations of faults in the main circuit, faults in the monitoring circuit, and the monitor output signal, it formulates probabilistic criteria for error detection, self-monitoring, and the reliability of positive and negative monitoring results. The analysis derives expressions showing how monitoring effectiveness depends on the method used, the fault-free operation probability of the monitoring circuit, and detection of simultaneous faults, and extends the criteria to systems capable of error correction.
Full Text
EFFICIENCY AND RELIABILITY OF INSTRUMENT-BASED MONITORING OF DIGITAL DEVICES
N. P. BAIDA
(Presented by the scientific seminar of the Department of Computer Engineering)
The most important quality indicators of instrument-based monitoring (IM) circuits for digital devices (DD)—efficiency [1–10] and reliability [11] of monitoring—are at present not clearly defined. To clarify these concepts, let us consider the set of different states of a DD with IM (Table 1). In what follows, by the efficiency of monitoring we shall understand the probability of detecting an error that has appeared in the main circuit (MC). Such a criterion of efficiency, in accordance with the terminology of operations research theory [12], most accurately reflects the objective facing the monitoring circuit (MCt)—to detect the maximum possible number of errors in the MC—and therefore has become the most widespread [5–10].
Table 1
| Event | State of the monitored circuit $A$ | State of the monitoring circuit $B$ | Reaction of the monitoring circuit $C$ | Note |
|---|---|---|---|---|
| $H_0$ | 0 | 0 | 0 | State of proper system operation |
| $H_1$ | 0 | 0 | 1 | Impossible event |
| $H_2$ | 0 | 1 | 0 | |
| $H_3$ | 0 | 1 | 1 | Determines $E_{\mathrm{self}}$ |
| $H_4$ | 1 | 0 | 0 | |
| $H_5$ | 1 | 0 | 1 | Determines $E_{\mathrm{m}}$ |
| $H_6$ | 1 | 1 | 0 | |
| $H_7$ | 1 | 1 | 1 |
In Table 1, the digit 0, depending on the column number, denotes the absence of errors in the MC ($\overline{A}$), in the monitoring circuit ($\overline{B}$), or the absence of an error signal at the MCt output ($\overline{C}$). The events $H_i$ $(i=\overline{0,7})$ determine the states of the system (in this case, by system we mean the combination of the main circuit and the IM circuit). For example, event $H_3$ means that the MC is in good working order, while there is an error in the monitoring circuit that is detected. Let us call the conditional probability $P(C/\overline{A}B)=E_{\mathrm{self}}$ the efficiency of self-monitoring, and $P(C/A\overline{B})=E_{\mathrm{m}}$ the efficiency of the monitoring method.
Analyzing Table 1, one can say that monitoring efficiency, as the probability of detecting an error that has appeared in the MC, is $P(C/A)$;
is determined by the events \(H_4—H_7\). Using the multiplication theorem for probabilities, one can write
\[ P(C/A)=\frac{P(AC)}{P(A)}. \tag{1} \]
According to Table 1,
\[ P(AC)=P(H_5)+P(H_7)=P(A\overline{B}C)+P(ABC). \tag{2} \]
Substituting (2) into (1) and taking into account that events \(A\) and \(B\) are independent, while event \(C\) depends on \(A\) and \(B\), we obtain
\[ \begin{aligned} \mathcal{E}=P(C/A) &=\frac{P(A\overline{B}C)+P(ABC)}{P(A)}= \\ &=\frac{P(A\overline{B})\cdot P(C/A\overline{B})+P(AB)\cdot P(C/AB)}{P(A)} = P(\overline{B})\cdot \mathcal{E}_{\mathrm{m}}+P(B)\cdot P(C/AB). \end{aligned} \tag{3} \]
It follows from this that the effectiveness of checking is determined by the effectiveness of the checking method, the probability of error-free operation of the checking circuit, and the probability of detecting multiple errors that occur simultaneously in the main and checking hardware.
In analyzing the reliability of IC, it is expedient to consider two criteria.
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\(D_1=P(A/C)\)—the reliability of a positive checking result (the probability that faults are present in the main circuit, if there is an error signal at the output of the checking circuit). Here and below, a fault is understood to mean a failure or malfunction of arbitrary multiplicity. It is assumed that a fault determines an error of the same multiplicity.
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\(D_0=P(\overline{A}/\overline{C})\)—the reliability of a negative checking result (the probability that faults are absent in the main circuit, if there is no error signal at the output of the checking circuit).
By Bayes’ formula we have
\[ \begin{aligned} D_1=P(A/C) &=\frac{P(A)\cdot P(C/A)} {P(A)\cdot P(C/A)+P(\overline{A})\cdot P(C/\overline{A})}= \\ &=\frac{P(A)\cdot P(C/A)} {P(A)\cdot P(C/A)+P(\overline{A})[1-P(\overline{C}/\overline{A})]}= \\ &=\frac{P(A)\cdot \mathcal{E}} {P(A)\cdot \mathcal{E}+P(\overline{A})-P(\overline{A})\cdot P(\overline{C}/\overline{A})}. \end{aligned} \tag{4} \]
The conditional probability \(P(\overline{C}/\overline{A})\) is the probability that a signal will not appear at the output of the checking circuit if there are no faults in the main circuit. By analogy with formulas (1–3), one can write
\[ P(\overline{C}/\overline{A}) =\frac{P(\overline{A}\,\overline{C})}{P(\overline{A})} =P(\overline{B})+P(B)(1-\mathcal{E}_{\mathrm{sam}}). \tag{5} \]
It follows from this that, in order to increase the probability \(P(\overline{C}/\overline{A})\), it is necessary to increase the probability of proper operation of the checking circuit and to reduce the “negative” influence of the effectiveness of self-checking. The latter can be achieved by introducing diagnostic tests that distinguish faults arising in the main and checking hardware. Then in (5), instead of \(\mathcal{E}_{\mathrm{sam}}\), it is necessary to consider
\[ \mathcal{E}_{\mathrm{sam}}^{*}=\mathcal{E}_{\mathrm{sam}}\cdot K_c, \tag{6} \]
where \(K_c\) is a coefficient showing what percentage of errors in the checking circuit causes the appearance of the “system failure” signal (Fig. 1).
The reliability of a negative control result is determined analogously to \(D_1\)
\[ D_0 = P(\bar{A}/\bar{C}) = \frac{P(\bar{A}) \cdot P(\bar{C}/\bar{A})} {P(\bar{A}) \cdot P(\bar{C}/\bar{A}) + P(A) \cdot P(A) \cdot \mathcal{E}} . \tag{7} \]
Fig. 1. Block diagram of the system
If IC makes it possible not only to detect but also to correct errors, then an additional efficiency criterion must be taken into account—the probability of correcting an error that has appeared in the main circuit (\(\mathcal{E}_{\mathrm{i}}\)). This criterion can also be calculated by formula (3), understanding by \(\mathcal{E}_{\mathrm{m}}\) and \(P(C/AB)\) the corresponding probabilities of error correction.
Conclusions
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An analysis has been carried out of the most important quality indicators of instrument-based control circuits for digital devices: the efficiency and reliability of control.
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As a result of the analysis, two efficiency criteria have been selected: the probability of detection and the probability of correction of an error that has appeared in the main circuit, and two reliability criteria: the reliability of positive and negative control results.
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On the basis of consideration of the state table of a control unit with IC, formulas have been derived for calculating the indicated criteria of the efficiency and reliability of control at the early stages of system design.
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