Introduction of New Operations into the Promin Electronic Digital Computer

V. M. Reider, G. N. Tarusin
Submitted 1974 | SovietRxiv: ru-197401.10587 | Translated from Russian

Abstract Generated abstract

This paper describes hardware modifications to the Promin electronic digital computer intended to mitigate its limited 100 cell command memory by replacing frequent command sequences with single new operations. The authors explain how unused combinations of operation codes and nonzero addresses are decoded to implement three added commands: a fixed addition followed by write, squaring, and cell clearing, using modified access to the microprogram matrix, trigger-controlled two-cycle execution, and added inverter, coincidence, flip-flop, and diode circuits. The described circuits allow common instruction groups to be compressed, thereby expanding the practical programming capabilities of the machine without a general enlargement of command memory.

Full Text

Introduction of New Operations in the “Promin” Electronic Digital Computer

V. M. Reider, G. N. Tarusin

(Presented by the scientific seminar of the computing laboratory)

As is known, an important shortcoming of the “Promin” machine is its small memory for storing commands—only 100 cells. Therefore, the principal developments carried out with the machine pursue the aim of expanding the capabilities of the program matrix. One possible way of solving this problem may be to replace frequently occurring combinations of commands by a single command or by a smaller number of them. This article gives descriptions of circuits for three newly introduced commands that replace the following groups of operations:

1. Read a     2. Read a     3. Read 00
   Add f 90      Multiply a    Write a
                 Write a

Since the operation codes for accessing the microprogram matrix, MPM, have no addresses, their combinations with addresses can be used to introduce new operations. Thus, to implement a new operation replacing the first combination of three commands, the operation code “arccosine” was used with an address different from zero; to obtain a new operation replacing the second combination, the operation code “square root” was taken with an address likewise different from zero. These two introduced operations are performed with the aid of almost the same functional elements, shown in Figs. 1 and 2.

Figure 1 gives the circuit of a decoder assembled on cells IV6Sh27a, IV6Sh27b, IV6Sh27v, which determines the state of the address register RA. If RA = 00, then a high potential from the output of IV6Sh27v permits access to the microprogram matrix for executing the operations “arccosine” and “square root.” With a nonzero address in RA, access to the microprogram matrix does not occur.

The execution of the new operations \(\arccos a\) and \(\sqrt a\) is carried out in two cycles. For this purpose the trigger TV3Sh28 (Fig. 2) is used; it inhibits the addition of “+1” to the command counter by pulse I2 in the first cycle and permits this addition in the second.

When the code \(\arccos\) appears in the operation register ROP and an address different from zero appears in RA, the potential \(S\) at the input of inverter IV6Sh22v will be negative, which in the first cycle is decoded as the operation Add F. On the other hand, the inverted potential \(\overline{S}\) blocks the out-

processing of pulse I2M by pulse I2. When memory is addressed for the Sl F operation, pulse IP O sets the mantissa adder to “0,” and IPP adds “+1” to the III decade of the mantissa adder. To avoid losing the address at which the result is written in the second cycle, the setting of RA to “0” by pulse IPT3 is blocked by the low level of potential \(S\). Then a fixed addition, Sl F, of one in the III decade of the mantissa adder to the contents of the address in RA is performed.

Fig. 1. Functional diagram of the \(\arccos a\) operation

Fig. 1. Functional diagram of the \(\arccos a\) operation

The end-of-operation pulse, generated upon completion of the addition, “flips” trigger TVZSh28 into the one state; in this case the low level of potential \(S\) is decoded as a “write” operation at the address in RA. Writing is performed according to the usual algorithm. In the second cycle of execution of the operation, the blocking of pulse I2 for adding “+1” to the command counter is removed.

Execution of the command “squaring” is performed using the code of the operation “square root” with a zero address in RA. In this case a negative potential \(y\) is produced, which in the first cycle is decoded as a “read” operation at the address in RA. In the second cycle, owing to the “flipping” of trigger TVZSh28, “multiplication” of the contents of the adder by the contents of the RA cell is performed.

As in the execution of the preceding operation, in the first cycle of the “squaring” command, pulse I2M is blocked and “+1” is entered into the command counter by pulse I2; in the second cycle the blocking of the entry of “+1” into the command counter is removed.

Fig. 2. Functional diagram of the operation \(Ua\)

For the operation “cell clearing,” which consists of two commands: 1. \(Cht\ 00\), 2. \(Zp\ a\), the operation code “hyperbolic sine” \(Sh\) with an address different from zero is used. (The functional diagram is shown in Fig. 3.)

Fig. 3. Functional diagram of the operation \(Sh\ a\)

When the code \(Sh\) appears in the operation register \(ROP\), and any address except zero appears in the address register \(RA\), access to the microprogram matrix \(MPM\) for executing \(Sh\) is blocked by the potential \(OO\ RA\). The code \(Sh\) is issued to the machine as \(Zp\) at the address specified in \(RA\). Execution of the operation \(Zp\ a\) proceeds according to the usual algorithm, except that the pulse \(IP1\), which rewrites the contents of the adder into the register, is blocked by the potential \(Sh\).

The circuit described in Fig. 3 operates in a machine in which the introduction of second-rank operations: \(Sl\ 11a\), \(Vych\ 11a\), \(Umn\ 11a\), and \(Del\ 11a\), allows operations with a code greater than 16 to be performed only when there is an asterisk \(*\) in the high-order digit of the register.

addresses. Therefore, to perform “cell clearing” operations, no additional blocking of access to the microprogram matrix was required. If the machine lacks blocking of access to the MPM when the address in RA is nonzero, it is not difficult to introduce it. For this purpose, it is necessary to set a high level OO RA in cell IV5Sh22a, which will prohibit the passage of pulse I2M for access to the microprogram matrix.

To implement the circuits shown in Figs. 1 and 2, it was necessary to use 4 new inverters, 7 coincidence circuits SP1, 1 flip-flop T, 3 coincidence circuits SP, and several D9E diodes.

In the circuit of Fig. 3, it was necessary to introduce three new inverters and one diode connecting the outputs IV5296 and IV5256.

In the figures, all additional new elements, unlike the old ones, have a double middle line.

The introduction of the three new operations described above, which replace frequently occurring combinations of commands, significantly expands the capabilities of the Promin machine.

Submission history

Introduction of New Operations into the Promin Electronic Digital Computer