Volume 246
1974

RESETTING THE UNITS OF ELECTRONIC DIGITAL COMPUTERS TO THE ZERO STATE

A. V. Trikhanov

(Presented by the Department of Computer Engineering)

Among known units, resetting to the zero state is performed in receiving and shifting registers, counters, and adders. In this process, the flip-flops of any unit are transferred to the zero state. For resetting a shifting register, a counter, or an adder, this is insufficient. The point is that, when a flip-flop is transferred to the zero state, a signal appears at its main output which, during shifting, counting, and summation, must be taken into account in the adjacent digit. On the other hand, during resetting this signal should not be taken into account.

To account for carry signals in units (with the exception of the counter), additional delay lines are used; in order to transfer the unit to the zero state, the delays must be reduced to zero. However, even in the absence of delay lines in the carry circuits of units, the carry signals enter adjacent digits with a certain small delay from the beginning of the transient process in the flip-flops under the action of the reset signal. Consequently, the operation of the units is unfavorable from the standpoint of transferring them to the zero state. In connection with this, special methods are used for resetting units.

The essence of these methods is that the flip-flop of a given digit, from the moment it passes into the zero state during the reset time \(\tau_{\mathrm{sb}}\), which is greater than the delay time of the signal in the circuit of one digit of the unit \(\tau_{\mathrm{zad}}\), should not change its zero state.

For a counter, \(\tau_{\mathrm{zad}}\) is equal to the time of the transient process in the flip-flop \(t_{\mathrm{tp}}\); for a shifting register and an adder, it is equal to the sum of the time \(t_{\mathrm{tp}}\) and the delay time in the delay line \(t_{\mathrm{zal}}\).

In [3] a review of existing methods for resetting counters is given, and their classification is presented. Existing methods for setting counters to the zero state are divided into three groups:

1) indirect methods,
2) methods based on neutralizing the action of carry signals,
3) methods based on blocking the transmission of carry signals.

Let us consider the application of these methods for resetting registers and adders. Indirect methods are characteristic of counters and require that a carry signal be applied to the counting input. If a counting input is used in adders, then in shifting registers the carry signal is applied to the one-setting input. However, the operability of the shifting-register circuit will not change if the carry signal is applied to the counting input [1]. The point is that, when the carry signal is received, the flip-flop is in the zero state and, consequently, when the carry circuit operates, the flip-flop will pass into the one state.

Methods for neutralizing the action of carry signals are applicable for setting any circuit to the zero position. The duration of the reset signal must be equal to \(\tau_{\mathrm{sb}}\). Methods for blocking the transmission of carry signals are also applicable for transferring any circuit to the zero position. If the blocking element is placed before the delay lines, then in shift registers and adders the setting of the zero state will be carried out exactly as in a counter. Thus, under certain conditions all existing reset methods are applicable to all units of an electronic digital computer.

In addition to the three groups indicated, one may propose a group of combined methods. The indirect method should be taken as the basis. The reset time of any \(n\)-digit unit by this method is equal to \(n\tau_{\mathrm{zad}} + t_{\mathrm{pp}}\). It is evident that the time for transferring a shift register or an adder to the zero state is approximately twice as large (under the condition that \(t_{\mathrm{zad}}\) and \(t_{\mathrm{pp}}\) are equal) as the reset time of a counter, which in itself is large. It is therefore important to reduce the time required to set a unit to the zero position. This can be achieved by additionally applying, for example, blocking of the action of carry signals. Let us divide the \(n\)-digit circuit of a unit into \(k\) identical parts. The number of digits \(m\) in a separate part will be equal to \(\frac{n}{k}\). Owing to the blocking of the action of carry signals from one part to another, a separate part may be regarded as an independent \(m\)-digit circuit. The reset time of such a circuit is equal to \(\frac{n}{k}\tau_{\mathrm{zad}} + t_{\mathrm{pp}} = \tau_{\mathrm{sb}}^{m}\). Let us investigate the dependence of the reset time of the entire circuit on the number of parts in it. If \(k = 1\), then \(m = n\). This means that there is no blocking in the circuit, and the time \(\tau_{\mathrm{sb}}^{m}\) is equal to the reset time of an \(n\)-digit circuit without blocking. If \(k = n\), then \(m = 1\). This means that blocking is present between all digits. In this case the entry of ones into the digits is unnecessary (the second term in the sum is not needed); it should be replaced by the entry of zeros. The time for setting the unit to the zero position becomes equal to \(\tau_{\mathrm{zad}}\), which occurs for resetting units only on the basis of blocking or neutralizing the action of carry signals.

An investigation of the dependence of the reset time of the entire circuit on the number of parts in it makes it possible to conclude that the proposed combined method is general, while the individual methods combined in it are special cases.

Of interest is the case when the number of parts is half the number of digits in the entire circuit. In this case a separate part consists of two digits. The time for transferring the unit to the zero position is equal to

\[ \tau_{\mathrm{sb}}^{2} = 2\tau_{\mathrm{zad}} + t_{\mathrm{pp}}. \]

The resetting of a part in this case can be performed differently—in two cycles. Instead of the indirect method, a sequential shift should be applied. In the first cycle zeros are entered into the odd digits of all parts; in the second cycle the even digits are reset and the action of carry signals from them is blocked. The time for setting the unit to the zero position \(\tau_{\mathrm{sb}}^{2*}\) will be equal to \(2\tau_{\mathrm{zad}}\).

This reset method should also be assigned to the group of combined methods.

References

1. E. A. Drozdov et al. Electronic Digital Computers. Oborongiz, 1968.

2. Laboratory Practicum for the Course “Discrete-Action Computing Machines,” ed. by N. A. Smirnov and V. B. Smolov. Vysshaya Shkola Publishing House, 1966.

3. A. V. Trikhanov, V. I. Kozhemyako. On the question of resetting a counter. Proceedings of TPI, vol. 230 (in press).