ON THE QUESTION OF POSSIBLE SCHEMES OF SHIFT REGISTERS BASED ON STATIC FLIP-FLOPS

A. V. TRIKHANOV

(Presented by the Department of Computer Engineering)

Registers, in addition to short-term storage of a number, are used to convert the serial code of a number into parallel code, and conversely, and also to shift a code by a definite number of digit positions to the right or to the left, which is necessary in normalizing numbers and in performing arithmetic operations on them.

A distinction is made between parallel-action registers and shift registers. Let us consider the question of possible schemes of binary shift registers based on static flip-flops. In doing so it should be borne in mind that, in some cases, the end digit positions freed during a shift either retain their previous states, or are filled with zeros, or receive new information from outside, while the information shifted out of the digit positions at the other end of the register is either lost or transmitted to external circuits.

When considering possible schemes of shift registers, it is sufficient to dwell on a shift by one digit position, since, as shown in [2], a register with a scheme for shifting by $m$ digit positions may be regarded as $m$ separate registers, in each of which there is a shift by one digit position; performing a shift by $m$ digit positions in the original register is equivalent to performing a shift by one digit position in all $m$ partial registers simultaneously.

In essence, the shift operation may be regarded as the transfer of the states of the register flip-flops to neighboring ones [3]. In this case, the signals for setting the new state of the flip-flops during a shift may be formed in various ways, six of which are described in [1–3].

The simplest shift scheme [2, 3] has the form shown in Fig. 1. This scheme operates on the principle of register quenching. To perform a single shift in it, a command pulse “quenching” is applied simultaneously to all flip-flops of the register. In this case, flip-flops that were in state “0” retain this state, while flip-flops that were in state “1” are reset. From the resulting change in the output voltage of the flip-flop, a pulse is formed which, through delay line DL, is applied to the one-input of the neighboring flip-flop. Thus the shift of ones in the register is carried out. The shift of zeros is then realized automatically, since no pulse is applied to the neighboring flip-flop from a flip-flop that was in the zero state. A drawback of the scheme considered is its low speed of operation.

operation due to double triggering of the element, the dependence of the shape of the carry pulse on the steepness of the leading edge of the flip-flop output voltage, and the need to break the carry lines when setting the register to zero.

Thus, in this circuit the shift is performed in two cycles: first all flip-flops of the register are set to “0,” and then, in those stages where necessary, ones are set. The delay lines must provide a delay of the pulses by one cycle.

A single-cycle shift circuit is shown in Fig. 2. In each stage there are two pulse-potential gates, \(V_n\). To perform a single shift, the “shift” command pulse is applied to all the gates.

Fig. 1. Register with parallel shift with formation of the carry signal by means of suppression

Fig. 2. Paraphase register with parallel shift

In each stage this pulse passes through one of the gates. Consequently, only one pulse can arrive at the flip-flop: either the pulse for transmitting “1,” or the pulse for transmitting “0.”

The delay lines in this circuit ensure separation between the instant at which the flip-flop state is read by the shift pulse and the instant at which the flip-flop is set to the new state under the action of signals arriving from the preceding flip-flop.

However, for real ratios between pulse durations, parasitic delays in the circuits, and the durations of the flip-flop fronts, delay lines are sometimes not needed. Of course, the reliability of the shift is reduced.

When the counting input of the flip-flop is used, another single-cycle shift circuit is realized [2]. A signal must be applied to this input only when the state of the flip-flop in the given stage does not coincide with the state of the flip-flop of the neighboring stage on the left.

In this case the state of the flip-flop of the given stage will change to the opposite one, i.e., this flip-flop will be set in accordance with the previous state of the neighboring stage on the left. In other cases there will be no change in the state of the flip-flop of the given stage. In the circuit, in the general case, delay lines are needed, but they may also prove superfluous (Fig. 3). This circuit was used in old machines, when potential logic elements were considerably simpler than pulse-potential gates, and counting inputs were in any case used in the flip-flops.

The pulse-potential gates in this circuit switch at the potential input half as often as in the preceding circuit. In addition, in this circuit there are fewer pulse-potential gates.

From the shift circuits considered, it follows that the principal difficulty encountered in constructing shifting registers is that, when a shift is performed, each stage must simultaneously both deliver information to the next stage and receive new information from the preceding stage. In the circuits considered, either there were delay lines for temporary storage of information, or

it was taken into account that the edges of the flip-flop output voltages are somewhat stretched and, consequently, the change in the output voltages lags somewhat behind the input signals. The latter in fact means that the short-term storage of information by parasitic capacitances is taken into account. If storage on reactances is not used, then to perform a shift in the register it is not enough to have one flip-flop per digit.

Fig. 3. Register with parallel shift with a change in the code of the number

Fig. 4. Register with parallel shift with formation of the carry signal in gates and quenching of the shift pulse

Another two-cycle circuit for performing a shift [1] has the form shown in Fig. 4. It differs from the two-cycle circuit with formation of carry signals by means of quenching (Fig. 1) by the presence of gates in the transfer circuit. The presence of gates eliminates the above-mentioned shortcomings of the circuit in Fig. 1.

In [3] a number of other shift-register circuits are described, among them two modifications of a circuit with two pulse-potential gates and two delay lines per digit: a modification operating on the principle of successive delay of the shift pulse (Fig. 5); a modification in which the indicated successive delay is implemented by means of the intrinsic delay of the gates (Fig. 6); a modification of a two-cycle circuit with quenching of the register and with gates between digits, operating on the principle of successive delay of the shift pulse (Fig. 7); and a two-cycle circuit operating on the principle of quenching a register flip-flop by a signal from the gate output (Fig. 8). The operation of the latter reduces to the following: the shift pulse interrogates the state of the flip-flop and, in the case when it corresponds to “1,” after passing through the gate, resets the flip-flop to “0,” and through the delay line writes the read “1” into the neighboring flip-flop.

Fig. 5. Paraphase register with sequential shift with delay of the shift pulse in delay lines

Fig. 6. Paraphase register with sequential shift with delay of the shift pulse in gates

Let us classify the existing circuits (Fig. 12). First of all, shift circuits may be classified according to the number of phases into single-phase (Figs. 2, 3, 5, 6) and two-phase (Figs. 1, 4, 7, 8).

Fig. 7. Register with serial shift, with formation of the carry signal in gates and quenching by the shift pulse

Fig. 8. Register with parallel shift, with quenching of the carry signal

Shifting registers may be either with parallel shift (Figs. 1, 2, 3, 4, 8) or with serial shift, operating on the principle of successive delay of the shift pulse (Figs. 5, 6, 7). Among the known circuits, not every shift method has circuits with serial shift. Such missing circuits are easy to compose. For a two-phase circuit with formation of carry signals by quenching the register, a variant with serial shift is shown in Fig. 9; for a shift with a change in the code of the number (the counting inputs are used), in Fig. 10; for a circuit in which the flip-flop is quenched by the carry signal, in Fig. 11.

Fig. 9. Register with serial shift, with formation of the carry signal by means of quenching

Fig. 10. Register with serial shift, with a change in the number code

Fig. 11. Register with serial shift, with formation of the carry signal in gates and quenching by the shift pulse

Single-phase circuits are divided into circuits with transmission chains of a two-position code (paraphase chains, Figs. 2, 5, 6), and into circuits operating on the principle of changing the code of the shifted number (Figs. 3, 10).

Both the former and the latter may have either parallel (Figs. 2, 3) or serial shift (Figs. 5, 6, 10).

Delays of shift signals in paraphase circuits with serial shifting are implemented either in delay lines (Fig. 5) or in gates (Fig. 6). This completes the classification of single-cycle shift registers. The single-cycle registers include five circuits, one of which (Fig. 10) was proposed by the author of the present article (the dashed rectangle) in the fourth row of the classification table.

Two-cycle circuits are divided into circuits with formation of carry signals in gates (Figs. 4, 7, 8, 11), and circuits with formation of carry signals by extinguishing flip-flops (Figs. 1, 9). Extinguishing the flip-flops of registers in a circuit with formation of carry signals in gates may be carried out either by the shift signal (Figs. 4, 7) or by the carry signal (Figs. 8, 11). All two-cycle registers perform shifting both in parallel fashion (Figs. 1, 4, 8) and serially (Figs. 7, 9, 11).

flowchart TB
    A[Shift registers]
    A --> B[Single-cycle]
    A --> C[Two-cycle]

    B --> D[Paraphase]
    B --> E[With change of the number code]

    D --> F[Parallel shift]
    D --> G[Serial shift]
    G --> H[With delay in delay lines]
    G --> I[With delay in gates]

    E --> J[Parallel shift]
    E --> K[Serial shift]

    C --> L[Formation of the carry signal in gates]
    C --> M[Formation of the carry signal by extinguishing]

    L --> N[Extinguishing by the carry signal]
    L --> O[Extinguishing by the shift pulse]
    N --> P[Parallel shift]
    O --> P

    M --> P
    M --> Q[Serial shift]

Fig. 12. Classification of shift registers based on static flip-flops

Of the circuits considered, six circuits belong to the two-cycle schemes, of which two (Figs. 9, 11) were proposed by the author of this work, as reflected by dashed lines in the classification table.

REFERENCES

1. E. A. Drozdov et al. Electronic Digital Computing Machines. Voenizdat, 1968.
2. M. A. Kartsev. Arithmetic of Digital Machines. Nauka, 1969.
3. Laboratory Practicum for the Course “Discrete-Action Computing Machines.” Vysshaya shkola, 1966.