BINARY-CODED DECIMAL ADDER-SUBTRACTOR FOR AUTOMATIC CONTROL SYSTEMS

N. P. Baida, E. B. Khilazhev

(Presented by the Department of Computer Engineering)

In modern automatic control systems (ACS), specialized computing devices (SCDs) are finding increasingly broad application; they make it possible to optimize the control process, perform self-checking of ACS, and determine the future state of the controlled object [1–3]. Usually such SCDs operate in the 8421 code and contain a binary-coded decimal adder as the main arithmetic unit. In this case, to perform decimal subtraction and division operations, it is necessary to obtain the complement code of the subtrahend.

However, the operation of obtaining the complement in the 8421 code is not reduced to simple inversion of the direct code of the subtrahend with the addition of one in the least significant digit, as in binary code, but is more complicated. To convert the direct decimal 8421 code into the complement, each decimal digit must be replaced by its complement to nine and one must be added in the least significant digit. The time required to obtain the complement in the 8421 code, when the arithmetic unit (AU) operates sequentially, is equal to the time for adding two numbers; moreover, when adding complementary decimal codes, the sum must be corrected just as when adding direct codes. As a result, in decimal subtraction in known SCDs, an additional operation of obtaining the complement is required, which lengthens the subtraction cycle twofold and reduces the speed of the AU. The operation of obtaining the complement can be eliminated if a binary-coded decimal adder-subtractor is used in the SCD as the main arithmetic unit; its functional diagram is shown in Fig. 1.

The binary-coded decimal adder-subtractor (DAS) contains a combinational binary adder-subtractor 1 for forming the initial uncorrected sum (difference), delay lines 2, 3 for delaying information by one clock cycle, a shift register 4 for four binary positions, which is used as a delay line for detecting the moment when correction begins, a decoder 5 for forming the signal indicating the need for correction, a flip-flop 6 storing the signal indicating the need for correction, coincidence circuits 7–10, which serve for strobing signals, an “OR” circuit, and a combinational binary adder-subtractor 12, identical to adder-subtractor 1 and serving to correct the initial sum (difference).

For operation of the BCD unit, synchronizing pulses (clock pulses) \(C_1, C_2, C_3, C_4\) (Fig. 2) are required, coinciding respectively with the fourth, third, second, and first digits of the tetrad, and control pulses \(H_1\) and \(H_2\).

Fig. 1. Functional diagram of the binary-coded decimal adder-subtractor:
1, 12 — combinational binary adder-subtractors; 2, 3 — delay lines; 4 — shift register; 5 — decoder; 6 — flip-flop; 7–10 — coincidence circuits

The numbers \(A\) and \(B\) in the 8421 code are applied to the circuit serially, least significant digits first, together with the “operating mode” signal (for addition \(R = 1\), for subtraction \(R = 0\)), and the synchronizing and control pulses. At the output of the BCD unit, the sum (difference)

\[ W = A \pm B \]

in the 8421 code is obtained.

Fig. 2. Basic timing relationships of BCD-unit operation.

When adding (subtracting) numbers in the 8421 code, it becomes necessary to correct the initial sum (difference). In serial operation of the device, sums greater than nine must be represented as one carry decimal into the higher digit and a remainder in binary-coded decimal code. All possible cases of binary sums greater than nine and their required representations are collected in the table.

If the state of the flip-flops in the binary digits is denoted by the symbols \(X_i\) \((i = 1, 2, \ldots 5)\), then, in terms of Boolean algebra, the condition for the necessity of correcting the result can be written in the form

\[ K = X_5 + X_4 (X_3 + X_2), \tag{1} \]

where

\(K\) — correction signal;
\(X_5\) — binary carry into the higher tetrad during addition, or borrow from the higher tetrad during subtraction.

In the proposed device, correction is performed by adding the code 0110 to the initial sum during addition or

by subtracting the code 0110 from the original difference during subtraction on the second binary adder-subtractor.

The operation of the combinational binary adder-subtractor is described in [14]. The numbers \(A\) and \(B\) in the 8421 code, least significant digits first, are applied to inputs 13 and 14 of binary adder-subtractor 1, and to input 15, the “operating mode” signal \(R\).

Table 1

Correction of intermediate sums

At the output of adder-subtractor 1 a binary sum (difference) is formed according to the formula

\[ W'_{\kappa}=P_{\kappa-1}(a_{\kappa}b_{\kappa}+\bar a_{\kappa}\bar b_{\kappa}) +\bar P_{\kappa-1}\overline{(a_{\kappa}b_{\kappa}+\bar a_{\kappa}\bar b_{\kappa})}, \]

where \(W'_{\kappa}\) is the binary digit of the sum (difference);

\(a_{\kappa}\) and \(b_{\kappa}\) are the binary digits of the numbers \(A\) and \(B\), respectively;

\(P_{\kappa-1}\) is the carry from the preceding binary digit during addition, or the borrow into the preceding binary digit during subtraction.

The carry signal into the next higher binary digit during addition, or the borrow from the highest binary digit during subtraction, is formed according to the formula

\[ P'_{\kappa}=R\,[a_{\kappa}b_{\kappa}+(a_{\kappa}+b_{\kappa})P_{\kappa-1}] +\bar R\,[\bar a_{\kappa}b_{\kappa}+(a_{\kappa}b_{\kappa}+\bar a_{\kappa}b_{\kappa})P_{\kappa-1}], \tag{3} \]

where

\[ R=1 \text{ during addition,} \]

\[ R=0 \text{ during subtraction.} \]

The binary carry (borrow) signal \(P'_{\kappa}\), through delay line 2 and assembly circuit, is applied to input 16 of binary adder-subtractor 1 for summation with the next binary digit in accordance with formula (2), and to decoder 5 for forming the correction signal. The uncorrected binary sum (difference) \(W'\) is fed from the output of adder-subtractor 1 through shift register 4 to input 13 of adder-subtractor 12, for algebraic summation with the correcting code 0110.

From the outputs of the flip-flops of shift register 4, the signals are applied to decoder 5, which forms the correction-necessity signal \(K\) according to formula (1). The correction-necessity signal \(K\), through a coincidence circuit—

of the drop 8, strobed by the control pulse \(И_2\), sets flip-flop 6 to “1,” and at the same time the signal \(K\), through coincidence circuit 7, strobed by pulse \(И_2\), and the “OR” circuit is applied to the input of adder-subtractor 1, effecting a decimal carry into the higher tetrad. Through coincidence circuit 9, prepared at one input by a signal from the one output of flip-flop 6, synchronizing pulses \(C_2 + C_3\), coinciding with the third and second digits of the tetrad, respectively, arrive at input 14 of adder-subtractor 12. By control pulse \(И_1\), flip-flop 6 is reset and, in the absence of signal \(K\), clock pulses \(C_2 + C_3\) will not pass through coincidence circuit 9 to input 14 of adder-subtractor 12. In this way the correcting code 0110 is formed.

Binary adder-subtractor 12 corrects the original sum (difference) \(W\) arriving at its input from shift register 4. In addition, when adding, the code 0110 is added to the original sum, and when subtracting, the code 0110 is subtracted from the original difference. The operation of adder-subtractor 12 is analogous to that of adder-subtractor 1. The binary carry (borrow) \(P\), delayed by one clock cycle by delay line 3, is added to the next binary digit of the tetrad. Decimal carry between tetrads when adding the code 0110 is inhibited by coincidence circuit 10. At the output of adder-subtractor 12 the correct sum (difference) \(W_i\) is formed in 8421 code.

Since, for correction in subtraction and addition in the decimal adder-subtractor, a single correcting code is used, the decimal adder-subtractor is more complex than a binary-decimal adder only due to the addition of equipment for implementing borrow logic during subtraction. However, eliminating the operation of obtaining the complement in decimal subtraction makes it possible to simplify the control circuit of the arithmetic unit significantly.

Therefore, using a binary-decimal adder-subtractor as the main arithmetic unit in automatic control systems makes it possible to increase the speed of decimal subtraction and division operations while simultaneously reducing the amount of equipment used.

REFERENCES

1. V. V. Somik, N. G. Kon’kov. An Automaton Checks an Aircraft and a Rocket. Moscow, Voenizdat, 1967.
2. M. D. Lebedev. The State and Development of Automatic Control Systems. Moscow, “Energiya,” 1968.
3. Electronics (trans. from English), No. 18, vol. 40, 1967.
4. Author’s certificate, No. 174 438, class 42m; 1403.