On the Control of a Reversible Counter
Abstract Generated abstract
The paper proposes a simple control method for reversible binary counters based on a property of their transition table: during correct addition or subtraction by one, exactly one counter digit undergoes the characteristic transition from 0 to 1 or from 1 to 0. The described circuit adds a control flip-flop, delay lines, and a coincidence circuit to verify that such a transition occurs after each counting pulse. If no required transition is detected, the circuit generates a failure signal, and an optional variant can also detect random failures between counting pulses. The method is presented as requiring relatively little additional equipment while simplifying control circuits for reversible counters.
Full Text
ON THE CONTROL OF A REVERSIBLE COUNTER
N. P. Baida
(Presented by the Department of Computer Engineering)
For the control of reversible binary counters, methods of control by numerical and digital modulus are used, as well as methods based on regularities in the alternation of states of the counting circuit \([1—4]\). Below a control method is described that follows from the features of the transition table of a reversible binary counter.
Suppose that the state of the counter at an arbitrary instant of time has the following form:
| No. of digit | \(1\ 2\ 3\ \ldots\ m-1\) | \(m\) | \(m+1\ \ldots\ n\) |
|---|---|---|---|
| State of digit | May be arbitrary | \(0\) | \(1\ \ldots\ 1\) |
When a “1” is added to the least significant digit, all digits that are to the right of \(m\) will pass from state “1” to state “0,” digit \(m\) will pass from state “0” to state “1,” and the remaining digits of the counter, located to the left of \(m\), will not change their state. The contents of the counter will increase by one, and the transition from state “0” to state “1” will occur in only one digit of the counter.
Similarly, when a “1” is subtracted from the least significant digit, the contents of the counter decrease by “1,” and the transition from state “1” to state “0” will occur in only one digit of the counter.
To control the operation of the counter, a control flip-flop \(1\) is added to its circuit (Fig. 1), which is set to state “1” (input \(S\)) by each counting pulse (input \(a\)).
The pulse arriving at the counting input \(b\) of the least significant digit of the counter is delayed on delay line \(2\) for the duration of the counting pulse.
Control flip-flop \(1\) is reset to state “0” (input \(R\)) in the event of a transition from state “0” to state “1” during addition (or from state “1” to state “0” during subtraction) in some digit of the counter. To form the reset signal, differentiating circuits or pulse shapers may be used (not shown in the drawing).
The count pulse, delayed by delay line 3 for the duration of the transient processes in the counter and the control flip-flop, is applied to one input of coincidence circuit 4. The signal from the one-output of control flip-flop 1 is applied to the other input of coincidence circuit 4.
Fig. 1. Functional diagram of control of a reversible counter
1 — control flip-flop; 2, 3 — delay lines; 4 — coincidence circuit;
\(a\) — count pulse; \(b\) — count input of the least significant digit of the counter being controlled; \(R\) — zero input of the control flip-flop; \(S\) — one-input of the flip-flop
If none of the counter flip-flops has changed over from state “0” to state “1” during addition, or from state “1” to state “0” during subtraction, then control flip-flop 1 remains in state “1,” and coincidence circuit 4 produces a failure signal, which is sent to the control device (not shown in the drawing).
To increase the effectiveness of control, a control flip-flop with a count input may be used, applying the counter transition signals and the count pulses through an “OR” circuit to the count input of the control flip-flop. In this case the control circuit will additionally detect random failures in the intervals between count pulses.
The method described requires only a small amount of control equipment and makes it possible to substantially simplify the control circuits of reversible counters.
REFERENCES
- V. N. Nomokonov, I. L. Erosh. Detection of failures in binary counting circuits by means of modulo checking. Izv. vuzov, “Priborostroenie,” No. 6, 1966.
- Inventor’s certificate No. 154 095, cl. 42m; 1403.
- Inventor’s certificate No. 217 456, cl. 21 a¹; 36/22.
- Inventor’s certificate No. 219 896, cl. 42m³; 11/00.