Proceedings of the Tomsk Order of the October Revolution and Order of the Red Banner of Labor Polytechnic Institute named after S. M. Kirov

Vol. 266　　　　　　　　　　　　　　　　　　　　　　　　　1976

ON THE ISSUE OF RESETTING THE RECEIVING REGISTER

A. V. Trikhanov, P. P. Grigoriev

(Presented by the scientific seminar of the Department of Computer Engineering)

In most cases of digital-to-analog conversion it is necessary that the receiving register retain a given code until the next one is received. In particular, this is necessary in the stepwise approximation of the results, read from magnetic tape, of the operation of an analog-to-digital converter. In this case the read results (binary codes) are fixed in the register and from it are fed to the input of the digital-to-analog converter.

This condition is satisfied by a register with paraphase entry [1]. One digit of such a register is shown in Fig. 1.

The signals for setting the flip-flop to the one state (У «1») and to the zero state (У «0») are implemented in accordance with the expressions:

\[ \text{У «1»} = x_i \cdot P; \]

\[ \text{У «0»} = \bar{x}_i \cdot P, \]

where \(P\) is the synchronizing signal,

\(\bar{x}_i, x_i\) are the direct and inverse values of the \(i\)-th digit of the binary code.

If \(x_i = 1\), then after the action of the signal \(P\) the signal У «1» is generated; if \(x_i = 0\), then У «0» is generated.

The implementation of this circuit on “Ural-10” modules, taking into account the specific form of the signals \(\bar{P}\) and \(\bar{x}_i\) taken from the outputs of the restoration amplifiers, is presented in Fig. 2.

In modules B2, B4 a flip-flop is assembled; module D is a two-input gate; modules B1 and B3 are inverters of the signals \(\bar{P}\) and \(\bar{x}_i\), respectively.

Fig. 1. Register digit with paraphase entry

Fig. 2. Register digit with paraphase entry on “Ural-10” modules

In accordance with the load capacity of module B, the inverter for \(P\) (module B1) can be used to control 2.5 modules D. Consequently, for one digit of the register, for inversion ...

this signal requires 0.4 of a module B. If, in terms of complexity, module D is regarded as equivalent to module B, then 4.4 modules are required for one register digit.

A more economical register circuit is proposed (Fig. 3), using the simultaneous application of the signals $\overline{P}$ and $\overline{x_i}$ to the B modules included in the flip-flop. The variant with simultaneous application differs from similar applications indicated in [2, 3] in that, unlike them, the signals begin simultaneously and end at different times. The reset signal $\overline{P}$ ends earlier.

During the action of the signals, the flip-flop connections are broken, and both of its halves are in the one state. After the reset signal ends, the connections are restored and the flip-flop is in the one state under the influence of the continuing action of the digit signal.

If, during the action of the reset signal, there is no digit signal, then the flip-flop is switched to the zero state.

Fig. 3. Register digit with simultaneous application of reset and entry signals

Taking into account the particular form of the signal $\overline{P}$ mentioned above, a circuit for generating the signal $\overline{P_1}$ on the basis of $\overline{P}$ should be used, as shown in Fig. 4.

As can be seen, the pulse $P_1$ is formed at the beginning of the signal $\overline{P}$; the pulse duration is determined by the capacitance of the capacitor connected to module Zh. If it is assumed that, in terms of complexity, this module is equivalent to two B modules, then, taking into account that the inverter B (Fig. 4) can be used in five register digits, for one register digit, in addition to the flip-flop modules, there are required

\[ \left(\frac{2}{n} + 0.2\right) \]

B modules, taking into account the flip-flop modules—$2.2 + \dfrac{2}{n}$ B modules. The ratio $\eta$ of the number of B modules for the known and proposed register circuits is equal to

\[ \eta=\frac{2.2}{1.1+\frac{1}{n}}=\frac{2.2n}{1.1n+1}. \]

Fig. 4. Reset-signal generation circuit

For large $n$, the one in the denominator may be neglected and, consequently, it may be assumed that $\eta=2$, i.e., under this condition the proposed circuit is twice as economical as the known one. For $n=8$, which is of interest when operating with the magnetic-tape storage unit of the M-220M machine, $\eta=1.8$. The dependence of $\eta$ on $n$ is shown in Fig. 5.

In Fig. 6 the operating diagrams of the proposed circuit are given. They take into account the mutual displacement of the signals at “1” and at “0.” For certain displacements

Fig. 5. Dependence $\eta=(n)$; $\eta$ is the ratio of the number of modules for the known and proposed circuits, $n$ is the number of digits in the register.

failures are observed in writing into the register. As can be seen from the diagrams, when the \(У\) “1” signal ends before the \(У\) “0” signal ends, the signal that has been read is lost. To reduce this possibility to a minimum, the duration of the \(У\) “0” signal should be decreased as much as possible, and the \(У\) “1” signals should be widened. In necessary cases, the \(У\) “1” signals must be delayed.

Fig. 6. Diagrams of the circuit operation

REFERENCES

1. B. V. Anisimov, V. N. Chetverikov. Fundamentals of the Theory and Design of Digital Computers. Moscow, “Mashinostroenie,” 1970.

2. B. M. Kogan, M. M. Kanevsky. Digital Computers and Systems. Moscow, “Energiya,” 1970.

3. A. G. Shigin. Digital Computers (Elements and Units). Moscow, “Energiya,” 1971.