A Method for Monitoring the Operability of a Shift Register
Abstract Generated abstract
The paper proposes a simplified device for monitoring the operability of a shift register when the period of shift pulses is stable. Instead of using a counter to measure the passage of a written one through the register, the method admits only the first shift pulse into a delay line and compares its delayed output with a differentiated signal produced when the one exits the opposite end of the register. With an appropriately chosen delay time, coincidence of these pulses produces a serviceability signal, while incorrect register operation prevents such a signal. The proposed arrangement uses two coincidence circuits, a delay line, and a differentiating stage, and is presented as simpler and potentially more reliable than counter-based monitoring.
Full Text
On One Method for Monitoring the Operability of a Shift Register
A. V. Trikhanov
(Presented by the scientific seminar of the Department of Computer Engineering)
A small number of devices for monitoring the operability of shift registers are known. Among them one should note the monitoring device [1], which uses the fact that a one written into some end stage of the register moves through the entire register in a certain number of shift pulses (within a certain time), which is counted by a counter; the monitoring device [2], based on comparing the value of a given stage after a shift with the value of the adjacent stage before the shift; and the monitoring device [3], in which the number of ones in the register is determined after each shift, taking into account those entering the register and those leaving it. The last two devices can also be used to monitor error detection during operation of the shift register together with other units of a computer; however, they are rather complex. The first device is the simplest.
If the period of occurrence of the shift pulses is stable, this device for monitoring the operability of a shift register can be substantially simplified by using a delay line instead of a counter and by ensuring that only the first shift pulse is supplied to the latter. As a result, the reliability of monitoring is also increased, since a delay line is a more reliable element than a counter.
The above-mentioned admission of the first pulse into the delay line is provided by a two-input coincidence circuit controlled by an end flip-flop of the register, into which a one is entered before monitoring.
The functional diagram of a device for monitoring the operability of a shift register with rightward shifting is shown in Fig. 1. It contains two-input coincidence circuits 1 and 2, a delay line \(D\), and a differentiating stage \(D_k\).
To check the operability of the register, shift pulses are applied to the zero inputs of all its flip-flops (to the shift bus) and to the input of coincidence circuit 1. Since, before the check, this circuit is opened by a one signal from the main output of the leftmost end flip-flop of the register, the first pulse will enter the delay line. After the delay time in this line, the indicated shift pulse will appear at one of the inputs of coincidence circuit 2; to the second input of this circuit, when a one leaves the shift register, there will be applied the negative signal obtained by differentiating the voltage drop at the zero output of the rightmost end flip-flop of the register.
With an appropriate choice of the delay time in the delay line, during correct operation of the shift register the negative pulses from the output of the delay line and from the output of the differentiating stage arrive simultaneously at the inputs of coincidence circuit 2; at the output of the latter a pulse appears—a serviceability signal. If the shift register operates incorrectly, there will be no serviceability signal.
The device described is, to some extent, analogous to the known device for monitoring the operability of a counter [4], which includes two multi-input coincidence circuits and a delay line. These coincidence circuits detect two states of the counter, each of which is the complement, up to the code \(11 \ldots 11\), of the other. These states, having a definite time shift relative to one another, repeat cyclically. There is no such regularity in the operation of a shift register.
Fig. 1. Functional diagram of a device for monitoring the operability of a shift register
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