Simulation of Digital Devices with Hardware Control in the LYAPAS Language

N. P. Baida, L. A. Lyadunkina, V. M. Razin

(Presented by the scientific seminar of the Department of Computer Engineering)

A component part of the problem of automating the design of hardware-control (HC) circuits for digital devices (DD) [1] is the task of automating the analysis and quality assessment of developed control circuits, which it is advisable to solve using the LYAPAS language [2]. In [3], general questions of modeling DDs in the LYAPAS language were considered for the purpose of verifying the operability of a device, and in [4] questions of modeling combinational DDs with HC in the BESM-4 computer language were considered for the purpose of evaluating the effectiveness and reliability of control. The present article is devoted to modeling both combinational and sequential DDs with HC in order to determine quantitative indicators, criteria of effectiveness and reliability of control.

As the DDs under study, known circuits of a binary decoder (BD) [4], a counter [5], and a pulse distributor [6] with HC were taken. The modeling was carried out according to the schematic and functional diagrams of the devices (Figs. 1–3) in accordance with the generalized block diagram of the programs (Fig. 4). The following conventional designations are introduced in the drawings:

\(B\) is a diode-capacitor gate (Fig. 2) that passes to the OR circuit differentiated pulses of only one polarity; \(t, u\) are the multiplicities of faults, respectively, in the main circuit and in the control circuit; \(h\) is the number of the input set in the complex of input signals \(C\) (\(B_2\) is the size of this complex); \(q\) is an error vector obtained using the “combination generator” operator and consisting of \(n\) ones and \(m-n\) zeros (\(n\) is the multiplicity of the fault, \(m\) is the number of elements of the circuit).

In modeling DDs with HC, faults of two types were taken into account: failures and malfunctions. Malfunctions of all elements except the flip-flop were modeled by inversion of the output signal, while malfunctions of the flip-flop were modeled by nonoperation or false operation at definite instants of time. A flip-flop model with faults is represented by the operator:

        165   0   0

§ 0   Aₐ ∧77 => c   ċ -22 ∘→6

\[ \begin{gathered} \S 1\quad c_0 \vee c_1 \neg \wedge A_\alpha \Rightarrow 11 \Rightarrow a,\\ f_{10}+c_{26}\Rightarrow c \Rightarrow d,\\ E_\alpha>27\Rightarrow b \qquad E>16\wedge c\Rightarrow c,\\ E_\alpha>5\wedge d\Rightarrow d \qquad A_\alpha\wedge c_{37}\mid \to 21\quad b\leftarrow\Rightarrow c,\\ \S 2\quad \beta\wedge c_b \circ \to 3\quad c_\alpha\vee \beta\Rightarrow \beta\to 5,\\ \S 3\quad \beta\wedge c_b \circ \to 4\quad c_\alpha \neg \wedge \beta\Rightarrow \beta\to 5,\\ \S 4\quad d\wedge c_d\Rightarrow a\quad \beta\neg\wedge a\circ \to 5 . \end{gathered} \]

Fig. 1. Schematic diagram of a decoder with HC.

\[ \begin{gathered} c_\alpha \oplus \beta \Rightarrow \beta,\\ \S 5\quad c\underline{\ }-2\circ \to 6\quad c_\alpha \oplus \beta \Rightarrow \beta,\\ c_\alpha \vee d \Rightarrow d,\\ \S 6. \end{gathered} \]

This operator, besides introducing faults, differs from that proposed in [3] in that it is considered not in isolation, while the result of its operation is determined by the change in the state of other elements.

schemes. For example, in a counter, when the next pulse arrives at the input of a flip-flop, the change in the state of the preceding flip-flop is analyzed. This analysis is performed by a differentiating circuit (§ 4), which reacts to a change of state \(1 \to 0\). Here \(d\) is a variable representing the state of the circuit at the preceding instant of time, before the arrival of the counting pulse.

If the flip-flop does not operate, the state of the circuit does not change; control from § 0 is transferred to § 6. In the event of false operation (§ 5), the application of an additional one to the counting input of the flip-flop is carried out.

Labels in the figure: “error signal”; “counting pulse.”

Fig. 2. Functional diagram of a binary counter with HC

Specifying a fault or a certain type of failure of some element of the circuit is performed by changing the code of this element in the main complex \(A\); for example, the code of flip-flop “1” in the \(L\)-operator considered is 22; for the case of nonoperation it is 20, and for false operation it is 24.

Failures of delay elements (DE) are assumed to be of two types: “G0” is a zero generator, when the element constantly has zero potential at its output (code 02), and “G1” is a one generator, when the element constantly has unit potential at its output (code 03). Normal operation of a delay element corresponds to code 01, and operation with faults to 04.

To simulate a delay line with faults, the \(L\)-operator is used:

\[ \begin{array}{ccc} 145 & 0 & 0 \end{array} \]

\[ \S 0\ c_{\alpha}\vee \beta \Rightarrow \beta\ c_{0}\vee c_{1}\,\urcorner \wedge A_{\alpha}>6 \]

\[ =\langle aA^{\alpha}<77-2c\to 1-1c\to 2-1 \]

\[ \begin{aligned} &\circ \to 4 - 1 \circ \to 3\\ &\S\ 1\quad \beta \land c_a \mid \to 4\\ &\S\ 2\quad c_a \oplus \beta = \to \beta \to 4\\ &\S\ 3\quad \beta \land c_a \circ \to 4 \to 2\\ &\S\ 4 \end{aligned} \]

The “NOT–OR” element with possible faults (proper operation corresponds to code 06, and improper operation to 07) is represented by the operator:

Figure labels (left diagram): error signal; clock pulses; \(DSh\).

Fig. 3. Functional diagram of a pulse distributor with hardware control.

Figure labels (right flowchart):

Preparation of working complexes and variables

Specification of multiplicities \(t, U = 0, 3\) and types of faults

\(t + U = 0\)

yes

no

\(0 \Rightarrow q\)

Specification of \(q\)

Changing the codes of the circuit elements

Specification of \(h\)

Direct simulation of the circuit

\(\Delta h \le B_2\)

yes

no

Have all \(q \ne 0\) been enumerated

yes

no

Have all \(t, U\) been considered

yes

no

Calculate and print the effectiveness and reliability of checking

Fig. 4. Flowchart of the simulation program for the control unit with hardware control.

\[ \begin{gathered} 156\quad 0\quad 0\\ \underline{\phantom{156}}\quad \underline{\phantom{0}}\quad \underline{\phantom{0}}\\ \S\ 0\ \#133\ a\ \underline{b}\ \|\\ \beta \land \underline{b}_1 \to 1 \qquad c_a \lor \beta = \to \beta\\ \S\ 1\quad \underline{A}_a \land c_{37}\circ \to 2 \qquad c_a \oplus \beta = \to \beta\\ \S\ 2. \end{gathered} \]

Here \(\underline{b}\) is a variable representing, in the space of all nodes of the circuit, the set of nodes connected to the inputs of the element being simulated (obtained as a result of executing the “mnouzel” operator [3]).

In a similar way, operation with faults in the “AND” and “OR” elements and in the diode-capacitor gate is simulated (Fig. 2, for transition

\(0 \longrightarrow 1\)—code 10, \(1 \longrightarrow 10\), code 11) is represented by the operator:

\[ \begin{gathered} \frac{163}{\phantom{163}}\quad \frac{0}{\phantom{0}}\quad \frac{0}{\phantom{0}}\\ \S\ 0\ \#133\ \alpha\ \underline{b}\parallel\ a\land \underline{b}\Rightarrow a\\ \underline{A}_{a}\land 77\Rightarrow b-11c\to 1-1\circ\to 2\\ \to 4\\ \S\ 1\quad a\neg\land\beta\circ\to 4\to 3\\ \S\ 2\quad \beta\neg\land\alpha\circ\to 4\to 3\\ \S\ 3\quad c_{a}\oplus\beta\Rightarrow\beta\\ \S\ 4\quad b-12\circ\to 5\quad c_{a}\oplus\beta\Rightarrow\beta\\ \S\ 5. \end{gathered} \]

Here the fault is assumed to be of the type of inversion of the output signal (code 12, § 4).

One of the principal operators in [3] is the “report” (donos), which determines the admissible sequence for simulating the elements of a circuit. However, in [3] this subprogram does not consider delay elements, since the assumption is made that the result of their operation is used only in the following cycle. Such an assumption is not always valid. For example, in the circuits of the counter (Fig. 2) and the distributor (Fig. 3), DEs must be included in the “report,” because the AND circuits connected to the DE outputs must operate at the end of the simulation cycle, when both their inputs have been prepared (i.e., after the delay time \(\tau\)). If the DE output is connected to a single-input element, then artificial devices are necessary in composing the “report” operator. For example, for the counter circuit (Fig. 2), the first element \(\gamma_{0}\) of the “report” element complex is assigned a control flip-flop (element number 20), which must operate twice in each cycle. The “report” operator for this circuit has the form:

\[ \begin{gathered} \frac{153}{\phantom{153}}\quad \frac{0}{\phantom{0}}\quad \frac{0}{\phantom{0}}\\ \S\ 0\quad \beta\Rightarrow c\Rightarrow d\quad 2\Rightarrow c\\ \S\ 1\quad 20\Rightarrow \gamma_{0}\\ \S\ 2\quad d\ x\ 3\ d\#133\ d\ b\parallel\\ \underline{b}\land c\to 2\quad d\Rightarrow \gamma_{c}\triangle c\\ c_{a}\oplus c\Rightarrow d\Rightarrow c\to 2\\ \S\ 3\quad c\Rightarrow B\gamma . \end{gathered} \]

In the process of simulating particular CUs (Figs. 1–3), other L-operators were also developed, which unify and supplement those described above. All of them can be easily modified.

The resulting set of L-operators can easily be applied to the simulation of registers and adders with HC. Owing to the hierarchical principle of programming in LYAPAS, programs can be composed for investigating the control circuits of complex CUs on the basis of an existing library of programs.

References

1. N. P. Baida, V. M. Razin. Automation of the design of hardware-control circuits for digital automata. First All-Union Conference on the Reliable Design of Digital Automata. Abstracts of papers. Kiev, 1971.

2. A. D. Cheredov, V. M. Razin, N. P. Baida. Algorithmic languages for modeling digital devices. Proceedings of TPI, vol. 266, Tomsk, 1976.

3. A. A. Utkin. Modeling relay circuits. In: A Logical Language for Representing Algorithms for the Synthesis of Relay Devices. Moscow, Nauka, 1966.

4. N. P. Baida, V. I. Naplekov, A. D. Cheredov. Modeling a decoder with hardware control on a universal digital computer. Proceedings of TPI, vol. 266, Tomsk, 1976.

5. N. P. Baida. A device for checking a binary counter. Information sheet No. 58–71, Tomsk, TsNTI, 1971.

6. N. P. Baida. A device for checking a sequence of pulses. Inventor’s certificate No. 337 782. Bulletin of Inventions, 1972, No. 15.