Analog-to-digital converter
Abstract Generated abstract
This article reviews analog-to-digital conversion methods for control and information-processing systems in which analog signals must be represented in digital code. It compares sequential counting, successive-approximation coding, and reading methods using accuracy, conversion speed, hardware volume, throughput, and an information-hardware efficiency criterion. On the basis of this comparison, the authors argue that different methods are preferable for different code lengths, and propose a binary-decimal converter structure that operates by sequential counting within each decimal digit and by digit-by-digit coding across digits. The proposed arrangement is presented as technically simple, sufficiently fast, and suitable for applications requiring rapid changes in measurement accuracy.
Full Text
UDC 681.3.05
ANALOG-TO-DIGITAL CONVERTER
V. I. Afonchenko, V. V. Medvedev, V. K. Yaselskii
(Submitted by the scientific seminar of the Faculty of Physics and Technology)
In most modern control and information-processing systems, digital computers are used; the solution of problems with their aid is carried out in digital (discrete) form, in the form of certain codes. Real objects, however—machines, production facilities, processes, etc.—often issue or receive information in analog form. In connection with this, a new direction has arisen in computer technology: the conversion of information from analog form into digital form and vice versa.
These converting devices are divided into two groups—ADCs and DACs. The present article considers the first group of converters: analog-to-digital converters.
At present, a classification of methods of analog-to-digital conversion has been adopted that is based on three classical conversion methods: sequential counting, successive-approximation coding, and reading. These methods are the most widely used in practice and are described in the greatest detail in the literature.
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The sequential-counting method is based on balancing the input (measured) quantity by a sum of standards (quanta) of minimum weight.
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The successive-approximation coding method makes it possible, when there are \(n\) standards whose “weights” in the binary system are, for example, proportional to powers of the number 2, to balance (measure) the input quantity by a set of standards corresponding to the input quantity.
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The reading method makes it possible, when there is a set of standards from the least, equal to one quantum, to the greatest, equal to \(2^n - 1\) quanta, and \(2^n - 1\) comparison circuits, to balance (measure) the input quantity with the corresponding standard.
Recently, all methods of analog-to-digital conversion have been reduced to one general and universal class, called the generalized scale method [1].
Methods of analog-to-digital conversion are compared according to the following criteria: accuracy, speed, and hardware characteristics. The accuracy of an ADC is determined mainly (apart from its dependence on the number of digits in the output code) by the magnitude of instrumental errors and is a consequence of the quality of operation of the analog units of the converter. Since approximately the same analog units are used for different conversion methods, it is possible
considered that the conversion accuracy depends only weakly on the adopted conversion method.
The second main criterion is speed, characterized by the duration of the conversion cycle \(T_{\mathrm{c}}\). The duration of the conversion cycle, unlike accuracy, depends both on the conversion method and on the number of digits in the converter output code (on the selected accuracy). From the analysis of the speed of various conversion methods carried out in [1], it follows that the counting method has the highest speed; moreover, its relative speed increases as the number of digits increases. This is due to the fact that, when the counting method is used, the duration of the conversion cycle does not depend on the number of digits.
An equally important criterion for evaluating the efficiency of a conversion method is the hardware characteristic. On the basis of the analysis of hardware characteristics carried out in [1], it can be concluded that the counting ADC has the largest amount of hardware. At \(n = 4\), the amount of hardware of a counting ADC is 5 times greater than that of a bit-by-bit coding ADC and 6 times greater than that of a successive-counting ADC. The analysis shows that the successive-counting ADC has the smallest amount of hardware.
An assessment of ADC efficiency from the standpoint of information theory is widely used—the throughput capacity of the ADC, determined by the expression [1]
\[ C=\frac{n}{T_{\mathrm{c}}}, \]
where \(n\) is the number of digits;
\(T_{\mathrm{c}}\) is the conversion-cycle time.
In a number of cases, a more general criterion for evaluating ADC efficiency is used—the information-hardware criterion.
\[ A=\frac{C}{N}, \]
where \(N\) is the number of components used in the ADC.
This criterion characterizes the amount of information passed by the ADC per unit time per unit of its equipment (per one component).
Graphs of the dependence of the relative information-hardware criterion on the number of digits \(n\) for three classical methods of constructing ADCs are given in Fig. 1. From the graphs of Fig. 1 it is seen that a counting ADC only for a small number of digits \(n \leq 4\) can be used with an efficiency approximately equal to that of a bit-by-bit coding ADC. As the number of digits increases, the efficiency of the counting ADC decreases. Comparison of the efficiency of a successive-counting ADC and a bit-by-bit coding ADC shows that, for a number of digits \(n \leq 8\), the successive-counting ADC is more efficient, while for \(n \geq 10\) the bit-by-bit coding ADC is more efficient. At \(n = 9\), these types of converters have the same efficiency.
From the analysis of the graphs considered it follows that, for a number of digits \(n < 9\), it is possible to create a converter having an efficiency value intermediate between the efficiency of a successive-counting ADC and that of a bit-by-bit coding ADC. Such a converter can be built using a binary-decimal code (to obtain a readout of the measured quantity in the decimal system).
A block diagram of one of the variants for constructing such a converter is presented in Fig. 2. In the figure the following are denoted:
CU — control unit;
CC — comparison circuit;
CCV — code-to-voltage converter (for compensation of the input quantity);
CR — code register.
The code register is a set of reversible decades (corresponding to the number of digits) and serves to form the code corresponding to the input (measured) quantity. The code-to-voltage converter generates a compensating voltage according to the code recorded in the code register. Since a sequential code is applied to the inputs of the reversible decade, the latter operates in the sequential-counting mode.
Fig. 1. Relative information-hardware criteria of ADCs
Fig. 2. Block diagram of an analog-to-digital converter
Thus, within a decimal digit the converter operates in the sequential-counting mode, and by decimal digits—as a digit-by-digit coding converter.
Such a converter may find application in scientific research and wherever it is necessary to change the accuracy (the number of count digits) promptly. In addition to providing the required accuracy, this converter has sufficient speed and can be easily implemented technically.
REFERENCES
- E. I. Gitis. Information converters for electronic digital computing devices. Moscow, “Energiya,” 1970.
- K. A. Netrebenko. Digital automatic compensators. Moscow, Gosenergoizdat, 1961.
- E. A. Drozdov, A. P. Pyatibratov. Automatic conversion and coding of information. Moscow, “Sovetskoe radio,” 1964.